M16C26 Datasheet, PDF (201/239 Pages) Renesas Technology Corp – 16-BIT CMOS SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/20 SERIES

Udenvdeelropment
Preliminary Specifications Rev. 0.9
Specifications in this manual are tentative and subject to change.
CPU Rewrite Mode (Flash Memory Version)
M16C/26 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Precautions on CPU Rewrite Mode
Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite mode.
(1) Operation speed
During CPU rewrite mode (EW0/EW1 mpde), set the BCLK as shown below using the main clock
divide ratio select bit (bit 6 at address 000616 and bits 6 and 7 at address 000716):
10.0 MHz or less when wait bit (bit 7 at address 000516) = 1 (with internal access wait state)
Note : Always perform it with a condition mentioned above.
(2) Instructions inhibited against use
The instructions listed below cannot be used during EW0 mode because they refer to the internal data
of the flash memory:
UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction
(3) Interrupts inhibited against use
The address match interrupt cannot be used during EW0 mode because they refer to the internal data
of the flash memory. If interrupts have their vector in the variable vector table, they can be used by
transferring the vector into the RAM area. The NMI and watchdog timer interrupts can be used to
automatically initialize the flash identification register and flash memory control register 0 to “0”, then
return to normal operation. However, these two interrupts' jump addresses are located in the fixed
vector table and there must exsist a routine to be executed. Since the rewrite operation is halted when
an NMI or watchdog timer interrupts occurs, you must reset the CPU rewite mode select bit to “1” and
the perform the erase/program operation again.
(4) How to access
For EW0 mode select bit and lock bit disable select bit to be set to “1”, the user needs to write a “0” and
then a “1” to it in succession. When it is not this procedure, it is not enacted in “1”. This is necessary
to ensure that no interrupt or DMA transfer will be executed during the interval. Also only when NMI
pin is “H” level.
(5) Writing in the user ROM area
If power is lost while rewriting blocks that contain the flash rewrite program with the CPU rewrite
mode, those blocks may not be correctly rewritten and it is possible that the flash memory can no
longer be rewritten after that. Therefore, it is recommended to use the standard serial I/O mode or
parallel I/O mode to rewrite these blocks.
(6) STOP/WAIT
Both instructions disrupt erase/program operation, and the state of the blocks operated upon is not
guaranteed. Inhibit these instructions when in CPU rewrite mode.
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