M16C26 Datasheet, PDF (130/239 Pages) Renesas Technology Corp – 16-BIT CMOS SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/20 SERIES

Udenvdeelropment
Preliminary Specifications Rev. 0.9
Specifications in this manual are tentative
Clock Synchronous Serial I/O Mode
and
subject to change.
SINGLE-CHIP 16-BIT
M16C/26 Group
CMOS MICROCOMPUTER
• Example of transmit timing (when internal clock is selected)
Tc
Transfer clock
1
Transmit enable
bit (TE)
0
Transmit buffer ¹
empty flag (Tl)
0
H
CTSi
L
CLKi
Data is set in UARTi transmit buffer register
Transferred from UARTi transmit buffer register to UARTi transmit register
TCLK
Stopped pulsing because CTS = H
Stopped pulsing because transfer enable bit = 0
TxDi
Transmit
1
register empty
flag (TXEPT)
0
Transmit interrupt ¹
request bit (IR) 0
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
Shown in ( ) are bit symbols.
Cleared to 0 when interrupt request is accepted, or cleared by software
The above timing applies to the following settings:
* Internal clock is selected.
* CTS function is selected.
* CLK polarity select bit = 0 .
* Transmit interrupt cause select bit = 0 .
Tc = TCLK = 2(n + 1) / fi
fi: frequency of BRGi count source (f1, f8, f32)
n: value set to BRGi
• Example of receive timing (when external clock is selected)
1
Receive enable
bit (RE)
0
1
Transmit enable
bit (TE)
0
Transmit buffer
1
empty flag (Tl)
0
H
RTSi
L
CLKi
Dummy data is set in UARTi transmit buffer register
Transferred from UARTi transmit buffer register to UARTi transmit register
1 / fEXT
Even if the reception is completed, RTS do not assert,
and it is asserted by readout of receive buffer register.
Receive data is taken in
RxDi
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5
Receive complete ¹
flag (Rl)
0
Transferred from UARTi receive register
to UARTi receive buffer register
Read out from UARTi receive buffer register
Receive interrupt ¹
request bit (IR) 0
Cleared to 0 when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings:
* External clock is selected.
* RTS function is selected.
* CLK polarity select bit = 0 .
fEXT: frequency of external clock
Meet the following conditions are met when the CLK
input before data reception = H
* Transmit enable bit 1
* Receive enable bit 1
* Dummy data write to UARTi transmit buffer register
Figure 1.15.12. Typical transmit/receive timings in clock synchronous serial I/O mode
124
Renesas Technology Corp.