M16C26 Datasheet, PDF (123/239 Pages) Renesas Technology Corp – 16-BIT CMOS SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/20 SERIES

Udenvdeelropment
Serial I/O
Preliminary Specifications Rev. 0.9
Specifications in this manual are tentative and subject to change.
M16C/26 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UART2 special mode register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2SMR2
Address
0376 16
When reset
X00000002
Bit
symbol
Bit name
IICM2 I²C mode select bit 2
Function
Refer to Table 1.15.14
CSC Clock-synchronous bit
SWC ^{SCL wait output bit}
0 : Disabled
1 : Enabled
0 : Disabled
1 : Enabled
ALS
SDA output stop bit
0 : Disabled
1 : Enabled
STAC ^{UARTi initialization bit}
0 : Disabled
1 : Enabled
SWC2 SCL wait output bit 2
0: UART2 clock
1: 0 output
SDHI SDA output disable bit
0: Enabled
1: Disabled (high impedance)
Nothing is assigned.
In an attempt to write to these bits, write 0 . The value, if read, turns out to be
indeterminate.
RW
UART2 special mode register 3
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2SMR3
Address
0375 16
When reset
000X0X0X2
Bit
symbol
Bit name
Function
RW
Nothing is assigned.
In an attempt to write to these bits, write 0 . The value, if read, turns out to be
indeterminate.
CKPH Clock phase set bit
0 : Without clock delay
1 : With clock delay
Nothing is assigned.
In an attempt to write to these bits, write 0 . The value, if read, turns out to be
indeterminate.
NODC Clock output select bit
0 : CLKi is CMOS output
1 : CLKi is N-channel open drain output
Nothing is assigned.
In an attempt to write to these bits, write 0 . The value, if read, turns out to be
indeterminate.
DL0 _{SDAi (TXDi) digital delay} b7 b6 b5
setup bit
0 0 0 : Without delay
(Note 1, Note 2)
0 0 1 : 1 to 2 cycle(s) of BRG count source
DL1
0 1 0 : 2 to 3 cycles of BRG count source
0 1 1 : 3 to 4 cycles of BRG count source
1 0 0 : 4 to 5 cycles of BRG count source
DL2
1 0 1 : 5 to 6 cycles of BRG count source
1 1 0 : 6 to 7 cycles of BRG count source
1 1 1 : 7 to 8 cycles of BRG count source
Note 1 : These bits are used for SDAi (TxDi)output digital delay when using UARTi for I²C interface.
Otherwise,must set to 0002 .
Note 2 : The amount of delay varies with the load on SCL and SDA pins. Also, when using an external clock, the amount of
delay increases by about 100 ns, so be sure to take this into account when using the device.
Figure 1.15.9. Serial I/O-related registers (6)
Renesas Technology Corp.
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