M16C26 Datasheet, PDF (55/239 Pages) Renesas Technology Corp – 16-BIT CMOS SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/20 SERIES

Udenvdeelropment
Preliminary Specifications Rev. 0.9
Specifications in this manual are tentative and subject to change.
Interrupts
M16C/26 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt Control
This section describes how to enable or disable maskable interrupts and how to set the priority to be
accepted. The discussion here does not apply to non-maskable interrupts.
Maskable interrupts are enabled or disabled using the interrupt enable flag (I flag), the interrupt priority
level selection bit, and the processor interrupt priority level (IPL). Whether an interrupt request is present
or absent is indicated by the interrupt request bit. The interrupt request bit and the interrupt priority level
selection bit are located in the interrupt control register of each interrupt. Also, the interrupt enable flag (I
flag) and the IPL are located in the flag register (FLG).
Figure 1.9.3 shows the configuration and memory map of the interrupt control registers.
49
Renesas Technology Corp.