M16C26 Datasheet, PDF (190/239 Pages) Renesas Technology Corp – 16-BIT CMOS SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/20 SERIES

Udenvdeelropment
Preliminary Specifications Rev. 0.9
Specifications in this manual are tentative
Flash Memory
and
subject to change.
SINGLE-CHIP 16-BIT
M16C/26 Group
CMOS MICROCOMPUTER
Outline Performance
Table 1.19.1 shows the outline performance of the M16C/26 (flash memory version).
Table 1.19.1. Outline performance of the M16C/26 (flash memory version)
Item
Flash memory operation mode
Performance
Three user modes (standard serial I/O, CPU rewrite, parallel I/O)
Erase block
division
User ROM area
See Figure 1.19.1
Write method
In units of word.
Erase method
Block erase
Erase/Write (E/W) control method E/W control by software command
Protect method
Two 8Kbyte user by register lock bit (FMR02)
Number of commands
5 commands
Erase/Write count (Notes 1, 2) Depends on device code (see Table 1.2b)
Data Retention
10 years
ROM code protect
Parallel I/O and standard serial I/O modes are supported.
Note 1: Block A and Block B are 10,000 times E/W. All other blocks are 1000 times E/W. (Under
development; mass production scheduled to start in the 3rd quarter of 2003.)
Note 2: Definition of E/W times:
The E/W times are defined to be per-block erasure times. For example, assume a case whereby a
4-Kbyte Block A is programmed one word at a time and erased once all 2048 write operations
have completed. In this case, the block is considered to have been written and erased once.
If a product is 100 times E/W, each block in it can be erased up to 100 times. When 10,000 times
E/W, Block A and Block B can each be erased up to 10,000 times. All other blocks can each be
erased up to 1000 times.
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Renesas Technology Corp.