M16C26 Datasheet, PDF (143/239 Pages) Renesas Technology Corp – 16-BIT CMOS SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/20 SERIES

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Preliminary Specifications Rev. 0.9
Specifications in this manual are tentative
Clock Asynchronous Serial I/O (UART) Mode
and
subject to change.
SINGLE-CHIP 16-BIT
M16C/26 Group
CMOS MICROCOMPUTER
Clock-Asynchronous Serial I/O Mode (used for SIM interface)
The SIM (Subscriber Identity Module) interface is used for connecting the microcomputer with a memory
card or the like; adding some extra settings in UART2 clock-asynchronous serial I/O mode allows the user
to use this function. Table 1.15.12 shows the specifications of clock-asynchronous serial I/O mode (used
for SIM interface).
Table 1.15.12. Specifications of clock-asynchronous serial I/O mode (used for SIM interface)
Item
Specification
Transfer data format
Transfer clock
Transmission/reception control
Other settings
Transmission start condition
Reception start condition
Interrupt request
generation timing
Error detection
• Transfer data 8-bit UART mode (bit 2, bit1, bit 0 of address 037816 = “1012”)
• One stop bit (bit 4 of address 037816 = “0”)
• With the direct format chosen
Set parity to “even” (bit 5, bit 6 of address 037816 = “112”)
Set data logic to “direct” (bit 6 of address 037D16 = “0”)
Set transfer format to LSB (bit 7 of address 037C16 = “0”)
• With the inverse format chosen
Set parity to “odd” (bit 5, bit 6 of address 037816 = “012”)
Set data logic to “inverse” (bit 6 of address 037D16 = “1”)
Set transfer format to MSB (bit 7 of address 037C16 = “1”)
• With the internal clock chosen (bit 3 of address 037816 = “0”) : fi / 16 (n + 1)
(Note 1) : fi = f1SIO, f2SIO, f8SIO, f32SIO (Do not set external clock)
• Disable the CTS and RTS function (bit 4 of address 037C16 = “1”)
• UART2 does not support sleep mode function.
• Set transmission interrupt factor to “transmission completed” (bit 4 of
address 037D16 = “1”)
• To start transmission, the following requirements must be met:
- Transmit enable bit (bit 0 of address 037D16) = “1”
- Transmit buffer empty flag (bit 1 of address 037D16) = “0”
• To start reception, the following requirements must be met:
- Reception enable bit (bit 2 of address 037D16) = “1”
- Detection of a start bit
• When transmitting
When data transmission from the UART2 transmit register is completed
(bit 4 of address 037D16 = “1”)
• When receiving
When data transfer from the UART2 receive register to the UART2 receive
buffer register is completed
• Overrun error (see the specifications of clock-asynchronous serial I/O) (Note 2)
• Framing error (see the specifications of clock-asynchronous serial I/O)
• Parity error (see the specifications of clock-asynchronous serial I/O)
- On the reception side, an “L” level is output from the TXD2 pin by use of
the parity error signal output function (bit 7 of address 037D16 = “1”)
when a parity error is detected
- On the transmission side, a parity error is detected by the level of input to
the RXD2 pin when a transmission interrupt occurs
• The error sum flag (see the specifications of clock-asynchronous serial I/O)
Note 1: ‘n’ denotes the value 0016 to FF16 that is set to. the UART2 bit rate generator.
Note 2: If an overrun error occurs, the UART2 receive buffer will have the nex. t data written in. In addition, the
UART2 receive interrupt request bit does not change.
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