M16C26 Datasheet, PDF (196/239 Pages) Renesas Technology Corp – 16-BIT CMOS SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/20 SERIES

Udenvdeelropment
Preliminary Specifications Rev. 0.9
Specifications in this manual are tentative and subject to change.
CPU Rewrite Mode (Flash Memory Version)
M16C/26 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Register Description
Figure 1.20.1 shows the flash identification register, flash memory control register 0 and flash memory
control register 1.
Flash memory control register 0 (FMR0):
Bit 0 of the flash memory control register 0 is the RY/BY status flag used exclusively to read the
operating status of the flash memory. During programming, erase, and erase-suspend operations, it
is “0”. Otherwise, it is “1”.
Bit 1 of the flash memory control register 0 is the CPU rewrite mode select bit. The CPU rewrite mode
is entered by setting this bit to “1”, so that software commands become acceptable. To set this bit to
“1”, it is necessary to write “0” and then write “1” in succession. To set this bit to “0” by only writing a
“0”.
Bit 2 of the flash memory control register 0 allows program and erase operations to occur on the two
8K byte user blocks. When this bit is set to "0", no program or erase operations can occur on these
blocks. To permit program and erase operations to occur on these blocks, set this bit to a "1". To set
this bit to “1”, it is necessary to write “0” and then write “1” in succession. This bit can be manipulated
only when the CPU rewrite mode select bit = “1” (Bit 1 of this register).
Bit 3 of the flash memory control register is the flash memory reset bit used to reset the control circuit
of the internal flash memory. This bit is used when exiting CPU rewrite mode and when flash memory
access has failed. When the CPU rewrite mode select bit is “1”, writing “1” for this bit resets the control
circuit. To release the reset, it is necessary to set this bit to “0” when RY/BY status flag is “1”. Also
when this bit is set to “1”, power is not supplied to the internal flash memory, thus power consumption
can be reduced. However, in this state, the internal flash memory cannot be accessed. To set this bit
to “1”, it is necessary to write “0” and then write “1” in succession when the CPU rewrite mode select
bit is “1”. Use this bit mainly in the low speed mode (when XCIN is the count source of BCLK).
It is not particularly necessary to set bit 3 of the flash memory control register 0 on return from STOP/
WAIT.
Figure 1.20.2c shows a flowchart for shifting to the low power dissipation mode. Always perform
operation as indicated in these flowcharts.
Bit 6 of the flash memory control register 0 is the program status flag used exclusively to read the
operating status of the auto program operation. If a program error occurs, it is set to “1”. Otherwise,
it is “0”.
Bit 7 of the flash memory control register 0 is the erase status flag used exclusively to read the
operating status of the auto erase operation. If an erase error occurs, it is set to “1”. Otherwise, it is “0”.
Figure 1.20.2a shows a EW0 mode set/reset flowchart, figure 1.20.2b shows a EW1 mode set/reset
flowchart. Always perform operation as indicated in these flowcharts.
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