M16C26 Datasheet, PDF (100/239 Pages) Renesas Technology Corp – 16-BIT CMOS SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/20 SERIES

Udenvdeelropment
Preliminary Specifications Rev. 0.9
Specifications in this manual are tentative
Three-Phase Motor Control Timer Function
and
subject to change.
SINGLE-CHIP 16-BIT
M16C/26 Group
CMOS MICROCOMPUTER
Three-Phase Motor Control Timer Function
Use of more than one built-in timer A and timer B provides the means of outputting three-phase motor
driving waveforms. This function requires that P85 become SD, making it important that P85 not be used for
general purpose I/O (GPIO). If the SD feature is not needed, then P85/SD must always be driven high.
Three-phase PWM control register 0 (Note 4)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
INVC0
Address
034816
When reset
0016
Bit symbol
Bit name
Description
RW
INV00
INV01
Effective interrupt output
polarity select bit
0: A timer B2 interrupt occurs when the
timer A1 reload control signal is 1 .
1: A timer B2 interrupt occurs when the
timer A1 reload control signal is 0 .
(Note 3)
Effective interrupt output 0: Not specified.
specification bit
1: Selected by the INV00 bit.
(Note 2)
(Note 3)
INV02
Mode select bit
0: Normal mode
(Note 4) ^{1: Three-phase PWM output mode}
INV03
Output control bit (Note 9) 0: Output disabled
1: Output enabled
(Note 10)
INV04
Positive and negative
0: Feature disabled
phases concurrent L output 1: Feature enabled
disable function enable bit
INV05
INV06
Positive and negative
0: Not detected yet
phases concurrent L output 1: Already detected
detect flag
(Note 5)
Modulation mode select
bit
0: Triangular wave modulation mode _{(Note 6)}
1: Sawtooth wave modulation mode _{(Note 7)}
INV07 Software trigger bit
0: Ignored
1: Trigger generated
(Note 8)
Note 1: Set bit 1 of the protect register (address 000A16) to 1 before writing to this register.
Note 2: Set bit 1 of this register to 1 after setting timer B2 interrupt occurrences frequency set counter.
Note 3: Effective only in three-phase mode 1(Three-phase PWM control register's bit 1 = 1 ).
Note 4: Selecting three-phase PWM output mode causes the dead time timer, the U, V, W phase output control circuits,
and the timer B2 interrupt frequency set circuit works.
Note 5: No value other than 0 can be written.
Note 6: The dead time timer starts in synchronization with the falling edge of timer Ai output. The data transfer from the
three-phase buffer register to the three-phase output shift register is made only once in synchronization with the
transfer trigger signal after writing to the three-phase output buffer register.
Note 7: The dead time timer starts in synchronization with the falling edge of timer A output and with the transfer trigger
signal. The data transfer from the three-phase output buffer register to the three-phase output shift register is
made with respect to every transfer trigger.
Note 8: The value, when read, is 0 .
Note 9: The INV03 bit is set to 0 in the following cases:
• When reset.
• When positive and negative go active simultaneously while INV04 bit is 1 .
• When set to 0 in a program.
• When input on the SD pin changes state from H to L . (The INV03 bit cannot be set to 1 when SD input is L .)
Note 10: When INV03 = 1 (three-phase motor control timer output enabled) P80, P81, P72, P73, P74, and P75 function
as U, U, V, V, W, and W.
Figure 1.14.1. Registers related to timers for three-phase motor control (1)
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Renesas Technology Corp.