M16C26 Datasheet, PDF (208/239 Pages) Renesas Technology Corp – 16-BIT CMOS SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/20 SERIES

Udenvdeelropment
Functions to
Preliminary Specifications Rev. 0.9
Specifications in this manual are tentative and
Inhibit Rewriting Flash Memory Version
subject to change.
SINGLE-CHIP 16-BIT
M16C/26 Group
CMOS MICROCOMPUTER
Functions To Inhibit Rewriting Flash Memory Version
To prevent the contents of the flash memory version from being read out or rewritten easily, the device
incorporates a ROM code protect function for use in parallel I/O mode and an ID code check function for
use in standard serial I/O mode.
ROM code protect function
The ROM code protect function is used to prohibit reading out or modifying the contents of the flash
memory during parallel I/O mode and is set by using the ROM code protect control address register
(0FFFFF16). Figure 1.21.1 shows the ROM code protect control address (0FFFFF16). (This address
exists in the user ROM area.)
If either bit of ROMCP1 is set to '0', ROM code protect level 1 is turned on, so that the contents of the flash
memory are protected against readout and modification.
If either bit of ROMCP2 is set to '0', ROM code protect level 2 is turned on, enabling additional protection
against readout and modification (such as by a production LSI tester). If both level 1 and level 2 are
enabled, level 2 is selected by default.
If both of the two ROM code protect reset bits are set to “00,” ROM code protect is turned off, so that the
contents of the flash memory version can be read out or modified. Once ROM code protect is turned on,
the contents of the ROM code protect reset bits cannot be modified in parallel I/O mode. Use the serial I/
O or some other mode to rewrite the contents of the ROM code protect reset bits.
ROM code protect control address
b7 b6 b5 b4 b3 b2 b1 b0
11
Symbol
ROMCP
Address
0FFFFF16
When reset
FF16
Bit symbol
Reserved bit
Bit name
Function
Always set this bit to 1.
ROMCP2
ROM code protect level 2
set bit (Note 1, 2)
b3 b2
00: Protect enabled
01: Protect enabled
10: Protect enabled
11: Protect disabled
ROMCR ^{ROM code protect reset}
bit (Note 3)
ROMCP1 ^{ROM code protect level}
1 set bit (Note 1)
b5 b4
00: Protect removed
01: Protect set bit effective
10: Protect set bit effective
11: Protect set bit effective
b7 b6
00: Protect enabled
01: Protect enabled
10: Protect enabled
11: Protect disabled
Note 1: When ROM code protect is turned on, the on-chip flash memory is protected against
readout or modification in parallel input/output mode.
Note 2: When ROM code protect level 2 is turned on, ROM code readout by a shipment inspection
LSI tester, etc. also is inhibited. Customers desiring to use ROM code protect level 2 should
first contact their Renesas technical support representative.
Note 3: The ROM code protect reset bits can be used to turn off ROM code protect level 1 and
ROM code protect level 2. However, since these bits cannot be changed in parall.el input/
output mode, they need to be rewritten in serial input/output or some other mode
Figure 1.21.1. ROM code protect control address
202
Renesas Technology Corp.