M16C26 Datasheet, PDF(154/239 Page) Renesas Technology Corp – 16-BIT CMOS SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/20 SERIES

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M16C26 Datasheet, PDF (154/239 Pages) Renesas Technology Corp – 16-BIT CMOS SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/20 SERIES

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Udenvdeelropment

Preliminary Specifications Rev.

Specifications in this manual are

UART2 Special Mode Register 4

0.9

tentative

and

subject to change.

SINGLE-CHIP 16-BIT

M16C/26 Group

CMOS MICROCOMPUTER

UART2 Special Mode Register 4

Bit 0 of UART2 special mode register 4 (address 037416) are used to start condition generate bit. When

the SCL, SDA output select bit (bit 3 of U2SMR4 register) is â1â and this bit is â1â, then the start condition

is generated.

Bit 1 of UART2 special mode register 4 are used to restart condition generate bit.

When the SCL, SDA output select bit (bit 3 of U2SMR4 register) is â1â and this bit is â1â, then the restart

condition is generated.

Bit 2 of UART2 special mode register 4 are used to stop condition generate bit.

When the SCL, SDA output select bit (bit 3 of U2SMR4 register) is â1â and this bit is â1â, then the stop

condition is generated.

Bit 3 of UART2 special mode register 4 are used to SCL, SDA output select bit.

Functions changed by these bits are shown in table 1.15.17 and figure 1.15.31.

Bit 4 of UART2 special mode register 4 are used to ACK data bit.

When the SCL, SDA output select bit (bit 3 of U2SMR4 register) is â0â and the ACK data output enable bit

(bit 5 of U2SMR4 register) is â1â, then the content of ACK data bit is output to SDA pin.

Bit 5 of UART2 special mode register 4 are used to ACK data output enable bit.

When the SCL, SDA output select bit (bit 3 of U2SMR4 register) is â0â and this bit is â1â, then the content

of ACK data bit is output to SDA pin.

Bit 6 of UART2 special mode register 4 are used to SCL output stop bit.

When this bit is â1â, SCL output is stopped at stop condition detection. (Hi-impedance status).

Bit 7 of UART2 special mode register 4 are used to SCL wait output bit.

When this bit is â1â, SCL output is fixed to "L" at falling edge of 10th bit of clock. When this bit is â0â, SCL

output fixed to âLâ is released.

148

Renesas Technology Corp.

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