M16C26 Datasheet, PDF (198/239 Pages) Renesas Technology Corp – 16-BIT CMOS SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/20 SERIES

Udenvdeelropment
Preliminary Specifications Rev. 0.9
Specifications in this manual are tentative and subject to change.
CPU Rewrite Mode (Flash Memory Version)
M16C/26 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Flash memory control register 0
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol
FMR0
Address
01B716
When reset
000000012
Bit symbol
Bit name
FMR00 RY/BY status flag
FMR01
EW entry bit
(Note 1)
FMR02
FMSTP
8Kbyte EW mode enable bit
(Note 2)
Flash memory reset bit
(Note 3, Note 5)
Reserved bits
FMR06 Program status flag (Note 6)
FMR07 Erase status flag (Note 6)
Function
RW
0: Busy (being written or erased)
1: Ready
0: Normal mode
(Software commands invalid)
1: EW mode
(Software commands acceptable)
0: EW mode disabled on 8Kbyte blocks
1: EW mode enabled on 8Kbyte blocks
0: Normal operation
1: Reset
Must always be set to 0
0: Pass
1: Error
0: Pass
1: Error
Flash memory control register 1
b7 b6 b5 b4 b3 b2 b1 b0
0 01
1
Symbol
FMR1
Address
01B516
When reset
0XX001012
Bit symbol
Reserved bit
Bit name
FMR11 EW mode select bit (Note 1)
Reserved bit
Function
Must always be set to "1"
0: EW0 mode
1: EW1 mode
Must always be set to "1"
Reserved bits
Must always be set to "0"
Nothing is assigned.
In an attempt to write to these bits, write 0. The value, if read, turns out to be
indeterminate.
FMR17
Blocks A and B access wait
bit (Note 7)
0: PM17 controls wait state insertion
1: Wait state inserted (1 wait)
RW
Flash memory control register 4
b7 b6 b5 b4 b3 b2 b1 b0
0
0000
Symbol
FMR4
Address
01B316
When reset
01000000 2
Bit symbol
Bit name
FMR40 Suspend enable (Note 1)
FMR41 Suspend request (Note 4)
Reserved bits
FMR46 Suspend status
Reserved bits
Function
0: Invalid
1: Valid
0: Erase restart
1: Suspend request
Must always be set to 0
0: Erase Active
1: Erase Inactive
Must always be set to 0
RW
Note 1: To set this bit to "1", write a "0" and then a "1" to it in succession. Make sure no interrupts or DMA
transfers occur before completion of these two write operations. While in EW0 mode, write to this
bit from a program located in other than flash memory.
Note 2: To set this bit to "1", first ensure that the CPU rewrite mode select bit is set = "1"; then write a "0"
followed by a "1" to FMR02 in succession. Make sure no interrupts or DMA transfers occur before
completion of these last two successive write operations. Additionally, bit FMR01 must also be set
to "1" prior to setting this bit to a "1".
Note 3: Effective only when the CPU rewrite mode select bit = "1". After writing "1", write "0" when RY/BY
status flag is "1".
Note 4: This bit becomes valid only when FMR40 = "1" and when in an erase operation.
• In EW0 mode, this bit can be set to "0" or "1" by program.
• In EW1 mode, this bit is automatically set to "1" when a maskable interrupt occurs. It can NOT be
set to "1" by program. (Writing "0" is available.)
Note 5: Write to this bit from a program in other than the flash memory.
Note 6: This flag is cleared to "0" by executing the Clear Status command.
Note 7: In cases where E/W cycles to Block A or B exceed 100 times (D7, D9, U7, U9), please set this bit
to "1" (with wait). When FMR17 is set to "1", one wait state is inserted per access to Block A or B -
regardless of the value of PM17. Wait state insertion during access to all other blocks, as well as
to internal RAM, is controlled by PM17 - regardless of the setting of FMR17.
Figure 1.20.1. Flash memory control registers 0, 1
192
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