M16C26 Datasheet, PDF (199/239 Pages) Renesas Technology Corp – 16-BIT CMOS SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/20 SERIES

Udenvdeelropment
Preliminary Specifications Rev. 0.9
Specifications in this manual are tentative and subject to change.
CPU Rewrite Mode (Flash Memory Version)
M16C/26 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
EW0 mode operation procedure
Program in ROM
Start
Single-chip mode, memory expansion
mode, or boot mode (Note 1)
Set processor mode register (Note 2)
Transfer CPU rewrite mode control
program to internal RAM
Jump to transferred control program in RAM
(Subsequent operations are executed by control
program in this RAM)
*1
Program in RAM
*1
(Boot mode only)
Set user ROM area select bit to 1
Set CPU rewrite mode select bit to 1 (by
writing 0 and then 1 in succession)(Note 3)
Using software command execute erase,
program, or other operation
(Set lock bit disable bit as required)
Execute read array command or reset flash
memory by setting flash memory reset bit (by
writing 1 and then 0 in succession) (Note 4)
Write 0 to CPU rewrite mode select bit
(Boot mode only)
Write 0 to user ROM area select bit (Note 5)
End
Note 1: In EW0 mode, must not be set to boot mode.
Note 2: During CPU rewrite mode, set the BCLK as shown below using the main clock divide ratio select bit (bit 6
at address 000616 and bits 6 and 7 at address 000716):
6.25 MHz or less when wait bit (bit 7 at address 000516) = 0 (without internal access wait state)
10.0 MHz or less when wait bit (bit 7 at address 000516) = 1 (with internal access wait state)
Note 3: For CPU rewrite mode select bit to be set to 1 , the user needs to write a 0 and then a 1 to it in
succession. When it is not this procedure, it is not enacted in 1 . This is necessary to ensure that no
interrupt or DMA transfer will be executed during the interval. Write to this bit only when executing out of
an area other than the internal flash memory. Also only when NMI pin is H level.
Note 4: Before exiting the CPU rewrite mode after completing erase or program operation, always be sure to
execute a read array command or reset the flash memory.
Note 5: 1 can be set. However, when this bit is 1 , user ROM area is accessed.
Figure 1.20.2a. EW0 mode set/reset flowchart
EW1 mode operation procedure
Program in ROM
Start
Single-chip mode or memory expansion mode
(Note 1)
Set processor mode register (Note 2)
Set EW1 mode select bit to 1 after
having set EW0 mode select bit to 1
(by writing 0 and then 1 in succession)(Note 3)
Using software command execute erase,
program, or other operation
(Set lock bit disable bit as required)
Write 0 to EW0 mode select bit
End
Note 1: In EW0 mode, must not be set to boot mode.
Note 2: During CPU rewrite mode, set the BCLK as shown below using the main clock divide ratio select bit (bit 6
at address 000616 and bits 6 and 7 at address 000716):
6.25 MHz or less when wait bit (bit 7 at address 000516) = 0 (without internal access wait state)
10.0 MHz or less when wait bit (bit 7 at address 000516) = 1 (with internal access wait state)
Note 3: For CPU rewrite mode select bit to be set to 1 , the user needs to write a 0 and then a 1 to it in
succession. When it is not this procedure, it is not enacted in 1 . This is necessary to ensure that no
interrupt or DMA transfer will be executed during the interval. Write to this bit only when executing out of
an area other than the internal flash memory. Also only when NMI pin is H level.
Note 4: Before exiting the CPU rewrite mode after completing erase or program operation, always be sure to
execute a read array command or reset the flash memory.
Note 5: 1 can be set. However, when this bit is 1 , user ROM area is accessed.
Figure 1.20.2b. EW1 mode set/reset flowchart
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