SDA9410-B13 Datasheet, PDF (83/179 Pages) Micronas – Display Processor and Scan Rate Converter using Embedded DRAM Technology Units

SDA9410
Preliminary Data Sheet
Output sync controller (OSCM/S)
5.7.3 Switching from H-and-V-freerunning to H-and-V-locked mode
In H-and-V-freerunning mode, generally, the phase of the generated synchronization
line-scanning pattern has no correlation to the input line-scanning pattern. A hard switch
from the H-and-V-freerunning mode to the H-and-V-locked mode therefore would cause
visible synchronization artefacts. To avoid these problems the SDA 9410 enlarges the
line and the field lengths of the output sync signals HOUT and VOUT in a defined
procedure to enable an invisible synchronization of the freerunning output to the input.
For vertical synchronization the maximum synchronization time is 260 ms for interlaced
and 520 ms for progressive display modes. Horizontal synchronization is performed in a
maximum time of 50 ms. To get the best performance it is recommended to change at
first the vertical and after the mentioned delay times the horizontal mode from free
running to locked.
5.7.4 Operation mode generator
The VOUT generator determines the VOUT signal. For proper operation of the VOUT
generator information about the line-scanning pattern sequence is necessary. The I²C
Bus parameters STOPMOM (STatic OPeration MOde Master), STOPMOS (STatic
OPeration MOde Slave) and the I²C Bus parameter ADOPMOM (ADaptive OPeration
MOde Master) define the line-scanning pattern sequence and the scan rate conversion
algorithms.
83
Micronas