SDA9410-B13 Datasheet, PDF (131/179 Pages) Micronas – Display Processor and Scan Rate Converter using Embedded DRAM Technology Units

SDA9410
Preliminary Data Sheet
I²C Bus
Sub address 0A
Bit
Name
D3...D2 YPEAKM
D1...D0 CPEAKM
Function
Vertical peaking factor for luminance signal master:
11: Factor 4
10: Factor 2
01: Factor 1
00: off
Vertical peaking factor for chrominance signal master:
11: Factor 4
10: Factor 2
01: Factor 1
00: off
Sub address 0B
Bit
Name
Function
D7
x
x
D6...D5 ^FORMATM
Input format master:
11: full CCIR 656
10: CCIR 656 only data, H- and V-sync according CCIR656
01: CCIR 656 only data, H- and V-sync according PAL/NTSC
00: 4:2:2
D4
FIEINVM Field polarity inversion master:
1: Field A=1, Field B=0
0: Field A=0, Field B=1
D3
VCRMODEM _{Input filtering of the incoming field signal master:}
1: on
0: off
D2...D1
NAPIPPHM _{Number of not active pixels from external HINM to the input data}
(LSBs of _{in system clocks of CLKM:}
NAPLIPM) _{Distance(HINM to input data) = (NAPIPDLM*4+NAPIPPHM+8)}
[NAPIPPHM = 0]
D0
TWOINM Chrominance input format master:
1: 2’s complement input (-128...127)
0: unsigned input (0...255)
inside the SDA 9410 the data are always processed as
unsigned data
131
Micronas