SDA9410-B13 Datasheet, PDF (172/179 Pages) Micronas – Display Processor and Scan Rate Converter using Embedded DRAM Technology Units

SDA9410
Preliminary Data Sheet
Operating range
Parameter
Symbol Min Nom Max Unit Remark
Input SYNCENS
Low time
t_WL
22
ns see "Timing
diagram clock" on
page 177
High time
Rise time
Fall time
Clock TTL Input X1/CLKD
t_WH
22
t_TLH
t_THL
ns
10 ns
10 ns
Clock frequency
1/T
27
MHz see "Timing
diagram clock" on
page 177
Low time
t_WL
10
ns
High time
t_WH
10
ns
Rise time
t_TLH
5 ns
Fall time
t_THL
5 ns
I²C Bus (All Values Are Referred To min(V_IH) And max(V_IL)), f_SCL = 400 KHz
High-Level Input Voltage
V_IH
3
5.25 V
see "I²C Bus timing
START/STOP" on
page 176
Low-Level Input Voltage
V_IL
0
1.5 V
see "I²C Bus timing
DATA" on
page 176
SCL Clock Frequency
Inactive Time Before Start Of Transmission
Set-Up Time Start Condition
Hold Time Start Condition
SCL Low Time
SCL High Time
Set-Up Time DATA
Hold Time DATA
SDA/SCL Rise Times
SDA/SCL Fall Times
Set-Up Time Stop Condition
Output valid from clock
Input filter spike suppression (SDA and SCL
pins)
Low-Level Output Current
f_SCL
t_BUF
t_SU;STA
t_HD;STA
t_LOW
t_HIGH
t_SU;DAT
t_HD;DAT
t_R
t_F
t_SU;STO
t_AA
t_SP
0
1.3
0.6
0.6
1.3
0.6
100
0
0.6
I_OL
400 kHz
µs
µs
µs
µs
µs
ns
µs
300 ns
300 ns
µs
900 ns
50 ns
3 mA
172
Micronas