SDA9410-B13 Datasheet, PDF (15/179 Pages) Micronas – Display Processor and Scan Rate Converter using Embedded DRAM Technology Units

SDA9410
Preliminary Data Sheet
Block diagram
YINM
UVINM
YINS
UVINS
INPUT PROCESSING MASTER
VERTICAL AND
HORIZONTAL
COMPRESSION/
HORIZONTAL
EXPANSION
VERT. PEAKING
3D
SPATIO
TEMPORAL
NOISE
REDUCTION
INPUT PROCESSING
SLAVE
VERTICAL AND
HORIZONTAL
COMPRESSION/
HORIZONTAL
EXPANSION
VERT. PEAKING
LETTER
BOX
DETECTION
eDRAM
MAIN
MEMORY
LINE TO
BLOCK
CONVERSION
MOTION
ESTIMATION
FILM MODE
DETECTION
OUTPUT PROCESSING MASTER
eDRAM
VECTOR
MEMORY
SCAN RATE CONVERSION
VERTICAL ZOOM
BLOCK TO
LINE
CONVERSION
OUTPUT PROCESSING SLAVE
MUX
SCAN RATE CONVERSION
DISPLAY PROCESSING
DLTI
DCTI
Y0
PEAKING
TRIPLE
DAC
U0
8:8:8
V0
INTERPOLATION
HINM
VINM
HINS
VINS
INPUT SYNC
CONTROLLER
MEMORY
CONTROLLER
Figure 2 Block diagram 2
OUTPUT SYNC
CONTROLLER
HOUT
VOUT
BLANK
15
Micronas