SDA9410-B13 Datasheet, PDF (53/179 Pages) Micronas – Display Processor and Scan Rate Converter using Embedded DRAM Technology Units

SDA9410
Preliminary Data Sheet
Application modes and memory concept
I²C Bus
parameter
PLLMOFF
1: off
0: on
PLLMRA
PLLSOFF
1: off
0: on
PLLSRA
PLLDOFF
1: off
0: on
PLLDRA
CLKOUTON
1: enabled
0: disabled
CLKMDEN
1: X1/CLKD
0: CLKM
Sub address
00h
00h
22h
22h
5Fh
5Fh
5Fh
5Fh
Description
PLLM master channel on or off, only for test purpose
PLLM range, only for test purpose
PLLS slave channel on or off, only for test purpose
PLLS range
PLLD display channel on or off, only for test purpose
PLLD range
Output of system clock CLKOUT
Input clock for PLLD
Table 36 Input write I²C Bus parameter
5.6
Application modes and memory concept
5.6.1 Introduction
The Main Memory of the SDA 9410 has an overall capacity of 6 Mbit. It is divided into
two identical and independent 3 Mbit parts.
The Main Memory has 2 completely independent data inputs (master and slave channel)
to enable a multitude of PIP features. In general the channels are asynchronous having
2 separate clock PLLs (CLKM, CLKS). Reading of master and slave data for display is
performed using a third asynchronous clock (CLKD). In this way a decoupling of input
and output clocks is achieved.
The Main Memory supports different operation modes of the SDA 9410 by adapted data
configurations. The different modes are defined by the I²C Bus parameter MEMOP (I²C
Bus sub address 53h).
53
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