SDA9410-B13 Datasheet, PDF (113/179 Pages) Micronas – Display Processor and Scan Rate Converter using Embedded DRAM Technology Units

SDA9410
Preliminary Data Sheet
Display processing
Table 93
ASCENTLTI
00
01
10
11
Amplitude
0.5
1
2
4
I²C Bus parameter ASCENTLTI
I²C Bus
parameter
THRESY
THRESY_UP
ASCENTLTI
Sub address
5Eh
5Eh
5Ch
Description
Defines lower sensitivity threshold of DLTI
Defines upper sensitivity threshold of DLTI
Defines amplitude of correction signal
Table 94 Output write I²C Bus parameters
5.12.3 Digital colour transition improvement
A new digital algorithm is implemented to improve horizontal transitions of the
chrominance signals resulting in a better picture sharpness. A correction signal
proportional to the slope of the detected horizontal transition of the input signal is added
to the original input signal. Different correction signals according to the bandwidth of the
input signal are selected. The amplitude of the correction signal is adjustable by the I²C
Bus parameter ASCENTCTI.
The exact position of a colour transition is calculated by detecting the corresponding zero
transition of the second derivative of both chrominance signals. Low pass filtering is
performed to avoid noise sensitivity. The I²C Bus parameter THRESC modifies the
sensitivity of the DCTI circuit. High values cause that only significant colour transitions
are improved. Small colour variations remain unchanged.
To eliminate “wrong colours” transitions, which are caused by over and undershoots at
the chroma transition, the sharpened chroma signals are limited to a proper value
automatically.
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