SDA9410-B13 Datasheet, PDF (80/179 Pages) Micronas – Display Processor and Scan Rate Converter using Embedded DRAM Technology Units

SDA9410
Preliminary Data Sheet
Output sync controller (OSCM/S)
I²C Bus parameter
[Default value]
MASTERON
[1]
Sub address
53h
SLAVEON
53h
[0]
Description
Display of master channel:
1: enabled
0: disabled
Display of slave channel:
1: enabled
0: disabled
Figure 36 Output write I²C Bus parameter
The next paragraphs describe the HOUT and VOUT generator in more detail. Both
generators have a so called “locked-mode” and “freerunning-mode”. Not all
combinations of the modi make sense. The table below shows ingenious configurations.
Mode
“H-and-V-locked”
“H-freerunning-V-locked”
“H-and-V-freerunning”
HOUTFR
0
1
1
VOUTFR
0
0
1
CLKMDEN
0
1
1
Figure 37 Ingenious configurations of the HOUT and VOUT generator
5.7.1 HOUT generator
The HOUT generator has two operation modes, which can be selected by the I²C Bus
parameter HOUTFR. The HOUT signal is active high (HOUTPOL=0) for 64 clock cycles
(X1/CLKD). In the freerunning-mode the HOUT signal is generated depending on the
PPLOP I²C Bus parameter. In the locked-mode the HOUT signal is locked on the
incoming H-Sync signal HIN. The polarity of the HOUT signal is programmable by the
I²C Bus parameter HOUTPOL. The BLANK signal can be used to mark the active part of
a line. To avoid transition artifacts of digital filters the number of active pixels can be
symmetrically reduced using the CAPPM and CAPPS I²C Bus parameter.
80
Micronas