SDA9410-B13 Datasheet, PDF (77/179 Pages) Micronas – Display Processor and Scan Rate Converter using Embedded DRAM Technology Units

SDA9410
Preliminary Data Sheet
Output sync controller (OSCM/S)
5.7
Output sync controller (OSCM/S)
Signals
HOUT
VOUT
BLANK
Pin number
4
5
7
INTERLACED
6
Description
horizontal synchronization signal (polarity programmable, I²C Bus
parameter 4Ah HOUTPOL, default: high active)
vertical synchronization signal (polarity programmable, I²C Bus
parameter 4Ah VOUTPOL, default: high active)
free programmable horizontal blanking signal (polarity
programmable, I²C Bus parameter 49h BLANKPOL, default: high
active)
interlaced signal (can be used for AC coupled deflection circuits)
Table 67 Output signals
The output sync controller generates horizontal and vertical synchronization signals for
the scan rate converted output signal. The figure below shows the block diagram of the
OSCM/S and the existing I²C Bus parameters.
HOUTPOL, HOUTFR, APPLOPD,
NAPOPD, BLANLEN, PPLOP, RMODE,
BLANDEL, HORPOSM, HORPOSS,
HORWIDTHM, HORWIDTHS, HOUTDEL
HIN
HOUT
generator
HOUT
BLANK
VIN
GMOTION,
MOVMO,
MOVPH,
MOVTYP
OPERATION
mode
generator
VOUT
generator
STOPMOM, STOPMOS, ^{VOUTPOL, VOUTFR,}
ADOPMOM
NALOPD, ALPFOPD,
LPFOP, VERPOSM,
VERPOSS, VERWIDTHM,
VERWIDTHS, INTMODE
VOUT
INTERLACED
Figure 34 Block diagram of OSCM/S
Furthermore the output sync controller derives framing signals from the generated
HOUT and VOUT for the output data processing. The framing signals depend on
different I²C Bus parameters. The whole output picture is a combination of three
channels:
77
Micronas