SDA9410-B13 Datasheet, PDF (30/179 Pages) Micronas – Display Processor and Scan Rate Converter using Embedded DRAM Technology Units

SDA9410
Preliminary Data Sheet
Input signal processing
5.4
Input signal processing
The Figure 12 shows a detailed block diagram of the input processing blocks. The input
signal can be vertically and horizontally compressed or horizontally expanded by a large
number of factors. Furthermore the input signal can be processed by different noise
reduction algorithms to reduce the noise in the signal. The noise measurement block
determines the noise level of the input signal. The letter box detection block finds the
start and end line of letter box pictures. The information can be used by a µC to calculate
zooming factors and to control the IC for resizing the picture for a full screen display on
16:9 tubes.
DELM
YINM
UVINM
NMLINE, NMALG NOISEME
Letter
box
detection
Noise
measurement
MASTER
Delay
-3/+4
Line
memories
Vertical and
horizontal
compression/
expansion
SNRON
NRON
Spatial noise
reduction
Temporal
noise
reduction
YM from Memory
YM to Memory
CM to Memory
CM from Memory
YINS
UVINS
Delay
-3/+4
Line
memories
SLAVE
Vertical and
horizontal
compression/
expansion
YS to Memory
CS to Memory
DELS
Figure 12 Block diagram of input processing blocks
The different blocks and the corresponding I²C Bus parameters will be described now in
more detail.
30
Micronas