SDA9410-B13 Datasheet, PDF (133/179 Pages) Micronas – Display Processor and Scan Rate Converter using Embedded DRAM Technology Units

SDA9410
Preliminary Data Sheet
I²C Bus
Sub address 10
Bit
Name
D7...D0 ALPFIPM
Function
Number of active lines per field in the input data stream master:
Active lines = ALPFIPM * 2 [ALPFIPM=144]
Sub address 11
Bit
Name
Function
D7...D2 VINDELM VINM input delay:
Delay(VINM to internal V-sync) = (128 * VINDELM + 1)*Tclkm
[VINDELM = 0]
D1
VINPOLM VINM polarity:
1: low active
0: high active
D0
HINPOLM HINM polarity:
1: low active
0: high active
Sub address 12
Bit
Name
D7
x
D6...D2 NALIPM
D1...D0 CHRFOR
M
Function
x
Number of not active lines per field in the input data stream
master:
Not active lines = NALIPM+3 [NALIPM= 20]
Chrominance Format Master Channel:
11: not defined
10: reserved
01: 4:2:0
00: 4:1:1
133
Micronas