SDA9410-B13 Datasheet, PDF (55/179 Pages) Micronas – Display Processor and Scan Rate Converter using Embedded DRAM Technology Units

SDA9410
Preliminary Data Sheet
Application modes and memory concept
1. line
4:2:2
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
U0
U2
U4
U6
V0
V2
V4
V6
4:1:1
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
U0
U4
V0
V4
4:2:0
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
U0
U2
U4
U6
V0
V2
V4
V6
2. line
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
U0
U2
U4
U6
V0
V2
V4
V6
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
U0
U4
V0
V4
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
3. line
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
U0
U2
U4
U6
V0
V2
V4
V6
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
U0
U4
V0
V4
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
U0
U2
U4
U6
V0
V2
V4
V6
Figure 25 Supported data formats
Additionally 3 fields of a decimated picture of the slave channel with the size of up to 1/
9 of the original format can be stored (4:1:1 or 4:2:0 format). In this mode motion
estimation and compensation (Micronas VDU algorithm) for the master channel is
supported (up to 30 MHz clock frequency). In parallel it is possible to insert the slave
channel at any display position using frame mode and without joint lines. Noise reduction
algorithm by recursive filtering is supported only for the master channel in SRC-Mode.
In SSC-Mode the data configuration of master and slave channel can be different.
Depending on the picture size it is possible to store only 1 field of luminance and
chrominance data or 2 fields. The data configuration can be defined by the I²C Bus
parameters ORGMEMM and ORGMEMS, respectively.
ORGMEMM
1
0
Data configuration of the memory
2 fields (limited picture size in SSC- and MUP-Mode)
1 field
Table 39 Definition of ORGMEM
ORGMEMS
1
0
Data configuration of the memory
3 fields PIP (SRC-Mode),
2 fields (restricted picture size, SSC and MUP Mode)
Slave channel blocked (SRC-Mode and ORGMEMM=1)
1 field (SSC- and MUP-Mode; SRC-Mode and ORGMEMM=0)
Table 40 Definition of ORGMEMS
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