SDA9410-B13 Datasheet, PDF (58/179 Pages) Micronas – Display Processor and Scan Rate Converter using Embedded DRAM Technology Units

SDA9410
Preliminary Data Sheet
Application modes and memory concept
Config.
1
2
3
4
5
6
7
8
9
10
11
12
Mode
SRC
SRC
SRC
SRC
SSC
SSC
SSC
SSC
MUP
MUP
MUP
MUP
Application
motion compensated up conversion (4:1:1 or 4:2:0) + PIP (ABAB, frame based)
motion compensated up conversion with enlarged picture size, no PIP facility
AABB conversion for master and slave channel, slave data is written twice (PIP-
and SSC-configuration)
used during switching from configuration 1 to configuration 7 without artefacts
2 independent not synchronized full size channels, AABB conversion
joint line free ’Double Window’ / ’Split Screen’ / ’PAP’ display, AABB conversion
display of 2 live channels, AABB conversion
slave channel exceeds the maximum double window size
display of 2 live channels, AABB conversion
master channel exceeds the maximum double window size
2 independent not synchronized full size channels, AABB conversion
high resolution Multi Picture for master and slave channel (one live picture possible)
AABB conversion
high resolution Multi Picture for master channel,
reduced resolution Multi Picture for slave channel, AABB conversion
reduced resolution Multi Picture for master channel,
high resolution Multi Picture for slave channel, AABB conversion
reduced resolution Multi Picture for master and slave channel, AABB conversion
Table 43 Applications of different data configurations
58
Micronas