SDA9410-B13 Datasheet, PDF (57/179 Pages) Micronas – Display Processor and Scan Rate Converter using Embedded DRAM Technology Units

SDA9410
Preliminary Data Sheet
Application modes and memory concept
5.6.2 Configuration controlling
The following Table 42 and Table 43 summarize all possible combinations of memory
data configurations for the master and slave channel and the corresponding
applications. The main configurations are no. 1 for motion compensated up conversion
and PIP insertion, no. 5 for joint line free Split Screen display and no. 9 for high quality
Multi Picture including one live channel.
Table 44 shows the possible picture sizes. The data formats can be always 4:2:0 or
4:1:1. In SSC and MUP mode the picture sizes are influenced by the I²C Bus parameters
MEMWRM and MEMWRS.
Config.
MEMOP
ORGMEMM
1
00
1
2
00
1
3
00
0
4
00
0
5
01
1
6
01
1
7
01
0
8
01
0
9
10
1
10
10
1
11
10
0
12
10
0
ORGMEMS
1
0
1
0
1
0
1
0
1
0
1
0
Master Channel Slave Channel
Fields
Fields
Y
C
Y
C
2
2
3
3
2
2
not available
1
1
3
3
2
2
1
1
1
1
2
2
2
2
2
2
1
1
1
1
2
2
1
1
1
1
2
2
2
2
2
2
1
1
1
1
2
2
1
1
1
1
Table 42 Programmable data configurations
57
Micronas