SDA9410-B13 Datasheet, PDF (51/179 Pages) Micronas – Display Processor and Scan Rate Converter using Embedded DRAM Technology Units

SDA9410
5.5
Clock concept
Preliminary Data Sheet
Clock concept
Signals
CLKM
CLKS
X1/CLKD
Pin number
18
58
2
Table 33 Input signals
Description
System clock input master channel
System clock input slave channel
System clock input display channel
Signals
CLKOUT
Pin number
3
Description
Clock output
Table 34 Output signals
The SDA 9410 supports different clock concepts. The Figure 24 shows a typical
application of the SDA 9410. The frontend clock is connected to CLKM input. The
second frontend clock is connected to CLKS input. The CLKOUT pin is connected to the
backend and the X1/CLKD input is connected to a crystal oscillator. The Figure 23
explains the clock switch, which may be used for the separate modes (see also Table
37 "Ingenious configurations of the HOUT and VOUT generator" on page 80).
CLKS
PLLS
CLKS_pll
CLKM
PLLM
CLKM_pll
0
X1/CLKD
1
PLLD
CLKD_pll
Figure 23
CLKMDEN
Clock concept of SDA 9410
CLKOUT
51
Micronas