SDA9410-B13 Datasheet, PDF (109/179 Pages) Micronas – Display Processor and Scan Rate Converter using Embedded DRAM Technology Units

SDA9410
Preliminary Data Sheet
Display processing
I²C Bus
parameter
VERINT
VPAN
Sub address
47h
54h
Description
Vertical expansion factor for master channel
Vertical adjustment of the output picture for master channel
Table 87 Output write I²C Bus parameter
5.12
Display processing
Signals
IY_O
IU_O
IV_O
Pin number
87
84
90
Description
Analog Y (luminance) output signal
Analog U (chrominance) output signal
Analog V (chrominance) output signal
Table 88 Output signals
The display processing part contains an integrated triple 9-bit DAC and performs digital
enhancements and manipulations of the digital video component signal. The figure
below shows the block diagram of the display processing part and the existing I²C Bus
parameters.
BCOF HCOF
CORING
THRESY
ASCENTLTI
YBORDERD
UBORDERD
VBORDERD
27 MHz
54 MHz
COARSDEL
DACEN
CHROM_AMP
YIN
CIN
8
Peaking
9
DLTI
9
9
9
Delay
9
Coarse
Delay
9
DAC
YO
+7/-8
OFC
Framing
8:8:8 ⁹
Delay
9
DAC
UO
8
Delay
8
DCTI
8
9
8
4:4:4 ₉
9
Delay
9
DAC
VO
Figure 52
THRESC
ASCENTCTI
Block diagram of display processing
109
Micronas