SDA9410-B13 Datasheet, PDF (126/179 Pages) Micronas – Display Processor and Scan Rate Converter using Embedded DRAM Technology Units

SDA9410
Preliminary Data Sheet
I²C Bus
7B
x
x
x
x
STATUS_SLA STATUS_ELA
A LBD
A LBD
RELY
LBD
TVMODEM
ISC
7C
x
x
x
x
x
x
NMSTATUS LBDSTATUS
TSNR
LBD
7D
x
x
x
x
x
x
x
TVMODES
ISC
7E
MOVMO
ME
MOVPH
ME
GMOTION
ME
MOVTYP MEMSTAT3 MEMSTAT2 MEMSTAT1 MEMSTAT0
ME
ME
ME
ME
ME
7F
x
x
x
x
x
x
x
SHIFTACT
MC
80
x
x
x
x
x
x
x
VIMSTATUS
I²C
81
x
x
x
x
x
x
x
VISSTATUS
I²C
82
x
x
x
x
x
x
x
OSSTATUS
I²C
x = don’t care
ISC - Input sync controller block
IFC - Input format conversion block
OSC - Output sync controller block
OFC - Output format conversion block
LBD - Letter box detection block
VHCOM - Vertical-horizontal compression/expansion block
TSNR - Temporal noise reduction block
ME - Motion estimation block
PK - Peaking
LTI - Luminance transition improvement block
CTI - Chrominance transition improvement block
CD - Coarse Delay block
MC - Memory controller
PLLM - Clock doubling block master
PLLS - Clock doubling block slave
PLLD - Clock doubling block display
I²C Bus block
126
Micronas