SDA9410-B13 Datasheet, PDF (27/179 Pages) Micronas – Display Processor and Scan Rate Converter using Embedded DRAM Technology Units

SDA9410
Preliminary Data Sheet
Input format conversion (IFCM/IFCS)
In case of CCIR 656 three modes are supported (FORMATM/FORMATS=11 means full
CCIR 656 support, including H-, V-Sync and Field signal, FORMATM/FORMATS=01
means only data processing, H- and V-Sync have to be added separately according
PAL/NTSC norm, FORMATM/FORMATS=10 means only data processing, H- and V-
sync have to be added separately according CCIR656-PAL/NTSC norm). The
representation of the samples of the chrominance signal is programmable as positive
dual code (unsigned, I²C Bus parameter TWOINM/TWOINS=0) or two's complement
code (TWOINM/TWOINS=1, "I²C Bus" on page 117, I²C Bus parameter 0Bh,2Dh).
Inside the SDA 9410 all algorithms assume positive dual code.
FORMATM/
FORMATS
00
01 (CCIR 656 only
data)
10
11 (full CCIR 656)
HINS/HINS
PAL/NTSC
PAL/NTSC
CCIR 656
x
VINM/VINS
PAL/NTSC
PAL/NTSC
CCIR 656
x
YINM/YINS
4:2:2
CCIR 656
CCIR 656
CCIR 656
UVINM/UVINS
4:2:2
x
x
x
Table 9
Input sync formats
The amplitude resolution for each input signal component is 8 bit, the maximum clock
frequency is 27 MHz. Consequently the SDA 9410 is dedicated for application in high
quality digital video systems.
27
Micronas