SDA9410-B13 Datasheet, PDF (81/179 Pages) Micronas – Display Processor and Scan Rate Converter using Embedded DRAM Technology Units

SDA9410
Preliminary Data Sheet
Output sync controller (OSCM/S)
I²C Bus
parameter
HOUTFR
1: free run
0: locked
mode
CAPPM
00: k = 0
01: k = 8
10: k = 16
11: k = 24
CAPPS
00: k = 0
01: k = 8
10: k = 16
11: k = 24
Sub address
4Ah
Description
HOUT generator mode select
46h
Reducing factor for the HORizontal WIDTH Master value of the
master channel
Number of active pixels per line = 8 * HORWIDTHM - 2*k
46h
Reducing factor for the HORizontal WIDTH Slave value of the master
channel
Number of active pixels per line = 8 * HORWIDTHM - 2*k
Table 68 Output write I²C Bus parameter
5.7.2 VOUT generator
The VOUT generator has two operation modes, which can be selected by the I²C Bus
parameter VOUTFR. The VOUT signal is active high (VOUTPOL=0) for two output lines.
In the freerunning-mode the VOUT signal is generated depending on the LPFOP I²C Bus
parameter.
In the locked-mode the VOUT signal is synchronized by the incoming V-Sync signal VIN
(means the internal VIN delayed by the I²C Bus parameter OPDELM, compare "Input
sync controller (ISCM/ISCS)" on page 22). The RMODE I²C Bus parameter (line-
scanning pattern mode 1: progressive, 0: interlaced) determines the scan rate
conversion mode. If RMODE=1, then for each incoming V-sync signal VIN an outgoing
V-sync signal VOUT has to be generated (e.g. 50 Hz interlaced to 50 Hz progressive
scan rate conversion). If RMODE=0, then during one incoming V-Sync signal, two VOUT
pulses have to be generated (e.g. 50 Hz interlaced to 100 Hz interlaced scan rate
conversion).
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Micronas