SDA9410-B13 Datasheet, PDF (134/179 Pages) Micronas – Display Processor and Scan Rate Converter using Embedded DRAM Technology Units

SDA9410
Preliminary Data Sheet
I²C Bus
Sub address 14
Bit
Name
D7...D6 x
D5...D1 NMLINE
D0
NMALG
Function
xx
Line for noise measurement (only valid for NMALG=1) [NMLINE
= 4]
Noise measurement algorithm:
1: measurement during vertical blanking period (line can be
defined by NMLINE)
0: measurement in the active picture
Sub address 15
Bit
Name
D7...D4 TNRCLY
D3...D0 TNRCLC
Function
Temporal noise reduction of luminance: classification
1111: slight noise reduction
:
0000: strong noise reduction
Temporal noise reduction of chrominance: classification
1111: slight noise reduction
:
0000: strong noise reduction
Sub address 16
Bit
Name
D7...D4 TNRKOY
D3...D0 TNRKOC
Function
Temporal noise reduction of luminance:
Vertical shift of the motion detector characteristic [TNRKOY=0]
Temporal noise reduction of chrominance:
Vertical shift of the motion detector characteristic [TNRKOC=0]
134
Micronas