SDA9410-B13 Datasheet, PDF (149/179 Pages) Micronas – Display Processor and Scan Rate Converter using Embedded DRAM Technology Units

SDA9410
Preliminary Data Sheet
I²C Bus
Sub address 44
Bit
Name
Function
D7...D0 BLANLEN Length of the signal BLANK in system clocks of X1/CLKD:
Length = 4 * BLANLEN [BLANLEN = 180]
Sub address 45
Bit
Name
Function
D7...D0 ^PPLOP(7...0) Number of pixels between two output H-syncs HOUT (only valid
for HOUTFR=1) in system clocks of X1/CLKD (Bit 7 to 0):
Number of pixels = 2 * PPLOP [PPLOP(7...0) = 176]
Sub address 46
Bit
Name
Function
D7...D5 x
xxx
D4
PPLOP(8) Number of pixels between two output H-syncs HOUT (only valid
for HOUTFR=1) in system clocks of X1/CLKD (Bit 8):
Number of pixels = 2 * PPLOP [PPLOP(8) = 1]
D3...D2 CAPPM
Reduces the active pixels per line of the master channel
(HORWIDTHM) at the output side = 8 * HORWIDTHM - 2 * k:
k=
24: CAPPM = 11
16: CAPPM = 10
8: CAPPM = 01
0: CAPPM = 00
D1...D0 CAPPS
Reduces the active pixels per line of the slave channel
(HORWIDTHS) at the output side = 4 * HORWIDTHS - 2 * k:
k=
24: CAPPS = 11
16: CAPPS = 10
8: CAPPS = 01
0: CAPPS = 00
149
Micronas