SDA9410-B13 Datasheet, PDF (29/179 Pages) Micronas – Display Processor and Scan Rate Converter using Embedded DRAM Technology Units

SDA9410
Preliminary Data Sheet
Input format conversion (IFCM/IFCS)
CLKM
SYNCENM
YINM
x
UVINM
x
y0
y1
y2
y3
u0
v0
u2
v2
YINMen
x
UVINMen
x
y0
y1
y2
y3
u0
v0
u2
v2
HINM/VINM
HINMen/VINMen
Figure 10 SYNCENM/SYNCENS signal
The Figure 11 shows the input timing and the functionality of the NAPIPDLM/NAPIPDLS
and NAPIPPHM/NAPIPPHS I²C Bus parameter in case of CCIR 656 and 4:2:2 parallel
data input format for one example. The signals HINMint, YINMint and UVMint are the
internal available sampled input signals.
CLKM
HINM
HINMint
CCIR 656 interface
YINM
YINMint
UVINMint
4:2:2 interface
YINM
UVINM
YINMint
UVINMint
xxx
u0 y0 v0 y1 u2 y2 v2 y3 u4 y4
(NAPIPDLM* 4 + NAPIPPHM + 7) * Tclkm
=(0 * 4 + 2 + 7) * Tclkm = 9 Tclkm (e.g.)
(NAPIPDLM* 4 + NAPIPPHM + 7) * Tclkm
=(0 * 4 + 3 + 7) * Tclkm = 10 Tclkm (e.g.)
u0
v0
u2
v2
u4
y0
y1
y2
y3
u0
v0
u2
v2
xxx
y0
y1
y2
y3
y4
xxx
u0
v0
u2
v2
u4
y0
y1
y3
y4
u0
v0
u2
v2
Figure 11 Input timing
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Micronas