SDA9410-B13 Datasheet, PDF (68/179 Pages) Micronas – Display Processor and Scan Rate Converter using Embedded DRAM Technology Units

SDA9410
Preliminary Data Sheet
Application modes and memory concept
Mode
SRC
SRC
SRC
SRC
SSC/
MUP
SSC/
MUP
SSC/
MUP
SSC/
MUP
Input
Master
Channel
625/50i
525/60i
625/50i
525/60i
625/50i
525/60i
625/50i
525/60i
Input
Slave
Channel
625/50i
525/60i
525/60i
625/50i
625/50i
525/60i
525/60i
625/50i
Output
Display
Channel
625/100i
625/50p
525/120i
525/60p
625/100i
625/50p
525/120i
525/60p
625/100i
625/50p
525/120i
525/60p
625/100i
625/50p
525/120i
525/60p
Comment
Motion compensation for master channel possible
Motion compensation for master channel possible
joint line free display for slave channel possible
(NEW)
joint line free display for slave channel possible
(NEW)
No motion compensation possible
No motion compensation possible
No motion compensation possible, no joint line
free display for slave channel possible
No motion compensation possible, no joint line
free display for slave channel possible
Table 61 Supported data formats
5.6.7 Master slave switch
This chapter describes the I²C Bus parameters used to execute a master and slave
exchange.
I²C Bus
parameter
[Default]
MASTSLA
[0]
MASLSHFT
[0]
Sub address
55h
56h
Description
Master / Slave shift:
1: Master and slave input signals are exchanged, reset of display
raster shift
0: Display raster is synchronized to input master channel (vertical
sync)
Master / Slave shift:
1: Display raster is shifted slave phase to prepare a master/slave
switch
0: Display raster is synchronized to input master channel (vertical
sync)
Table 62 Input write I²C Bus parameter
68
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