SDA9410-B13 Datasheet, PDF (128/179 Pages) Micronas – Display Processor and Scan Rate Converter using Embedded DRAM Technology Units

SDA9410
Preliminary Data Sheet
I²C Bus
Sub address 03
Bit
Name
Function
D4...D2 RIBORDM Amount of right border pixels by horizontal compression
master: 4*RIBORDM [RIBORDM=0]
D1...D0 CHFILM
Chrominance Filter Master channel on/off
11: vertical and horizontal filter on (only valid for
DEZHM=DEZVM=0)
10: horizontal filter on (only valid for DEZHM=0)
01: vertical filter on (only valid for DEZVM=0)
00: off
Sub address 04
Bit
Name
Function
D7...D5 DELM
Adjustable delay between luminance and chrominance data
master channel:
111:+4
110:+3
101:+2
100:+1
011: 0
010: -1
001: -2
000: -3
D4
FORCOLM _{Force colour master channel}
1: on
0: off
D3...D0 ^YBORDERM Y border value (Yborder(3) Yborder(2) Yborder(1) Yborder(0) 0
0 0 0 = 00010000 = 16), YBORDERM defines the 4 MSB’s of a
8 bit value
128
Micronas