PIC16F707 Datasheet, PDF (97/284 Pages) Microchip Technology – 40/44-Pin, Flash Microcontrollers with nanoWatt XLP and mTouch™ Technology

PIC16F707/PIC16LF707
REGISTER 12-1: OPTION_REG: OPTION REGISTER
R/W-1
RBPU
bit 7
R/W-1
INTEDG
R/W-1
TMR0CS
R/W-1
TMR0SE
R/W-1
PSA
R/W-1
PS2
R/W-1
PS1
R/W-1
PS0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual PORT latch values
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of INT pin
0 = Interrupt on falling edge of INT pin
TMR0CS: TMR0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (FOSC/4)
TMR0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
PS<2:0>: Prescaler Rate Select bits
BIT VALUE TMR0 RATE WDT RATE
000
1:2
1:1
001
1:4
1:2
010
1:8
1:4
011
1 : 16
1:8
100
1 : 32
1 : 16
101
1 : 64
1 : 32
110
1 : 128
1 : 64
111
1 : 256
1 : 128
TABLE 12-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
INTCON
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
OPTION_REG RBPU INTEDG TMR0CS TMR0SE
PSA
PS2
PS1
TMR0
Timer0 Module Register
TRISA
TRISA7 TRISA6 TRISA5 TRISA4
TRISA3
TRISA2 TRISA1
Legend: – = Unimplemented locations, read as ‘0’. Shaded cells are not used by the Timer0 module.
Bit 0
Value on
POR, BOR
Value on
all other
Resets
RBIF
PS0
0000 000x 0000 000x
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
TRISA0 1111 1111 1111 1111
 2010 Microchip Technology Inc.
Preliminary
DS41418A-page 97