PIC16F707 Datasheet, PDF (144/284 Pages) Microchip Technology – 40/44-Pin, Flash Microcontrollers with nanoWatt XLP and mTouch™ Technology

PIC16F707/PIC16LF707
FIGURE 18-5:
RX/DT pin
Rcv Shift
Reg
Rcv Buffer Reg
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
ASYNCHRONOUS RECEPTION
Start
bit _{bit 0 bit 1}
Start
bit 7/8 Stop bit bit 0
bit
Word 1
RCREG
Start
bit 7/8 Stop bit
bit
Word 2
RCREG
bit 7/8 Stop
bit
Note:
This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
TABLE 18-2: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
ANSELC
INTCON
PIE1
PIR1
RCREG
RCSTA
SPBRG
TRISC
TXSTA
Legend:
ANSC7 ANSC6 ANSC5
—
—
ANSC2 ANSC1 ANSC0 111- -111
GIE
PEIE TMR0IE INTE
RBIE TMR0IF INTF
RBIF 0000 000x
TMR1GIE ADIE
RCIE
TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000
TMR1GIF ADIF
RCIF
TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000
AUSART Receive Data Register
0000 0000
SPEN
RX9
SREN CREN ADDEN FERR OERR RX9D 0000 000x
BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000
TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111
CSRC
TX9
TXEN SYNC
—
BRGH TRMT TX9D 0000 -010
x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for asynchronous reception.
111- -111
0000 000x
0000 0000
0000 0000
0000 0000
0000 000x
0000 0000
1111 1111
0000 -010
DS41418A-page 144
Preliminary
 2010 Microchip Technology Inc.