PIC16F707 Datasheet, PDF (175/284 Pages) Microchip Technology – 40/44-Pin, Flash Microcontrollers with nanoWatt XLP and mTouch™ Technology

PIC16F707/PIC16LF707
19.2.10 CLOCK SYNCHRONIZATION
When the CKP bit is cleared, the SCL output is held
low once it is sampled low. Therefore, the CKP bit will
not stretch the SCL line until an external I²C master
device has already asserted the SCL line low. The
SCL output will remain low until the CKP bit is set and
all other devices on the I²C bus have released SCL.
This ensures that a write to the CKP bit will not violate
the minimum high time requirement for SCL
(Figure 19-14).
19.2.11 SLEEP OPERATION
While in Sleep mode, the I²C module can receive
addresses of data, and when an address match or
complete byte transfer occurs, wake the processor
from Sleep (if SSP interrupt is enabled).
FIGURE 19-14: CLOCK SYNCHRONIZATION TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDA
SCL
CKP
WR
SSPCON
DX
Master device
asserts clock
Master device
deasserts clock
DX-1
 2010 Microchip Technology Inc.
Preliminary
DS41418A-page 175