PIC16F707 Datasheet, PDF(58/284 Page) Microchip Technology – 40/44-Pin, Flash Microcontrollers with nanoWatt XLP and mTouch™ Technology

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

PIC16F707 Datasheet, PDF (58/284 Pages) Microchip Technology – 40/44-Pin, Flash Microcontrollers with nanoWatt XLP and mTouch™ Technology

◁

PIC16F707/PIC16LF707

6.3.4.4 RB3/AN9/CPSB11/CCP2

These pins are configurable to function as one of the

following:

â¢ General purpose I/O

â¢ Analog input for the ADC

â¢ Capacitive sensing input

â¢ Capture 2 input, Compare 2 output, and PWM2

output

Note: CCP2 pin location may be selected as

RB3 or RC1.

6.3.4.5 RB4/AN11/CPSB12

These pins are configurable to function as one of the

following:

â¢ General purpose I/O

â¢ Analog input for the ADC

â¢ Capacitive sensing input

6.3.4.6 RB5/AN13/CPSB13/T1G/T3CKI

These pins are configurable to function as one of the

following:

â¢ General purpose I/O

â¢ Analog input for the ADC

â¢ Capacitive sensing input

â¢ Timer1 gate input

â¢ Timer3 clock input

6.3.4.7 RB6/ICSPCLK/CPSB14

These pins are configurable to function as one of the

following:

â¢ General purpose I/O

â¢ In-Circuit Serial Programming clock

â¢ Capacitive sensing input

6.3.4.8 RB7/ICSPDAT/CPSB15

These pins are configurable to function as one of the

following:

â¢ General purpose I/O

â¢ In-Circuit Serial Programming data

â¢ Capacitive sensing input

TABLE 6-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Value on all

other

Resets

ADCON0

ANSELB

APFCON

CCP2CON

CPSBCON0

CPSBCON1

INTCON

IOCB

â

ANSB7

â

â

CPSBON

â

GIE

IOCB7

â

ANSB6

â

â

CPSBRM

â

PEIE

IOCB6

CHS3

ANSB5

â

DC2B1

â

â

TMR0IE

IOCB5

CHS2

ANSB4

â

DC2B0

â

â

INTE

IOCB4

CHS1

ANSB3

â

CCP2M3

CPSBRNG1

CPSBCH3

RBIE

IOCB3

CHS0

ANSB2

â

CCP2M2

CPSBRNG0

CPSBCH2

TMR0IF

IOCB2

GO/DONE

ANSB1

SSSEL

CCP2M1

CPSBOUT

CPSBCH1

INTF

IOCB1

ADON --00 0000

ANSB0 1111 1111

CCP2SEL ---- --00

CCP2M0 --00 0000

TBXCS 00-- 0000

CPSBCH0 ---- 0000

RBIF 0000 000x

IOCB0 0000 0000

--00 0000

1111 1111

---- --00

--00 0000

00-- 0000

---- 0000

0000 000X

0000 0000

OPTION_REG

PORTB

T3CON

T1GCON

RBPU INTEDG

RB7

RB6

TMR3CS1 TMR3CS0

TMR1GE T1GPOL

TMR0CS

RB5

T3CKPS1

T1GTM

TMR0SE

RB4

T3CKPS0

T1GSPM

PSA

RB3

â

T1GGO/

DONE

PS2

RB2

T3SYNC

T1GVAL

PS1

RB1

â

T1GSS1

PS0

RB0

TMR3ON

T1GSS0

1111 1111

xxxx xxxx

0000 -0-0

0000 0x00

1111 1111

xxxx xxxx

0000 -0-0

uuuu uxuu

TRISB

WPUB

Legend:

TRISB7 TRISB6 TRISB5 TRISB4

TRISB3

TRISB2

TRISB1 TRISB0 1111 1111

WPUB7 WPUB6 WPUB5 WPUB4 WPUB3

WPUB2

WPUB1 WPUB0 1111 1111

x = unknown, u = unchanged, - = unimplemented locations read as â0â. Shaded cells are not used by PORTB.

1111 1111

1111 1111

DS41418A-page 58

Preliminary

ï£ 2010 Microchip Technology Inc.

▷