PIC16F707 Datasheet, PDF (96/284 Pages) Microchip Technology – 40/44-Pin, Flash Microcontrollers with nanoWatt XLP and mTouch™ Technology

PIC16F707/PIC16LF707
12.1 Timer0 Operation
The Timer0 module can be used as either an 8-bit timer
or an 8-bit counter.
12.1.1 8-BIT TIMER MODE
The Timer0 module will increment every instruction
cycle, if used without a prescaler. 8-bit Timer mode is
selected by clearing the TMR0CS bit of the OPTION
register.
When TMR0 is written, the increment is inhibited for
two instruction cycles immediately following the write.
Note:
The value written to the TMR0 register can
be adjusted, in order to account for the two
instruction cycle delay when TMR0 is
written.
12.1.2 8-BIT COUNTER MODE
In 8-bit Counter mode, the Timer0 module will increment
on every rising or falling edge of the T0CKI pin. 8-bit
Counter mode using the T0CKI pin is selected by setting
the TMR0CS bit of the OPTION register to ‘1’.
The rising or falling transition of the incrementing edge
for either input source is determined by the TMR0SE bit
in the OPTION register.
12.1.3 SOFTWARE PROGRAMMABLE
PRESCALER
A single software programmable prescaler is available
for use with either Timer0 or the Watchdog Timer
(WDT), but not both simultaneously. The prescaler
assignment is controlled by the PSA bit of the OPTION
register. To assign the prescaler to Timer0, the PSA bit
must be cleared to a ‘0’.
There are 8 prescaler options for the Timer0 module
ranging from 1:2 to 1:256. The prescale values are
selectable via the PS<2:0> bits of the OPTION register.
In order to have a 1:1 prescaler value for the Timer0
module, the prescaler must be assigned to the WDT
module.
The prescaler is not readable or writable. When the
prescaler is enabled or assigned to the Timer0 module,
all instructions writing to the TMR0 register will clear the
prescaler.
Note:
When the prescaler is assigned to WDT, a
CLRWDT instruction will clear the prescaler
along with the WDT.
12.1.4 TIMER0 INTERRUPT
Timer0 will generate an interrupt when the TMR0
register overflows from FFh to 00h. The TMR0IF
interrupt flag bit of the INTCON register is set every
time the TMR0 register overflows, regardless of
whether or not the Timer0 interrupt is enabled. The
TMR0IF bit can only be cleared in software. The
Timer0 interrupt enable is the TMR0IE bit of the
INTCON register.
Note:
The Timer0 interrupt cannot wake the
processor from Sleep since the timer is
frozen during Sleep.
12.1.5 USING TIMER0 WITH AN
EXTERNAL CLOCK
When Timer0 is in Counter mode, the synchronization
of the T0CKI input and the Timer0 register is
accomplished by sampling the prescaler output on the
Q2 and Q4 cycles of the internal phase clocks.
Therefore, the high and low periods of the external
clock source must meet the timing requirements as
shown in Section 25.0 “Electrical Specifications”.
12.1.6 TIMER ENABLE
Operation of Timer0 is always enabled and the module
will operate according to the settings of the OPTION
register.
12.1.7 OPERATION DURING SLEEP
Timer0 cannot operate while the processor is in Sleep
mode. The contents of the TMR0 register will remain
unchanged while the processor is in Sleep mode.
DS41418A-page 96
Preliminary
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