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| PIC16F707 Datasheet, PDF (100/284 Pages) Microchip Technology – 40/44-Pin, Flash Microcontrollers with nanoWatt XLP and mTouch™ Technology | |||
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PIC16F707/PIC16LF707
FIGURE 13-1:
TxGSS<1:0>
TIMER1/TIMER3 BLOCK DIAGRAM
TxG
00
TxGSPM
FrOomveTrfilmowe(r4A)/B
01
From Timer2
Match PR2
10
From WDT
Overflow
11
TxGPOL
Set flag bit
TMRxIF on
Overflow
TxG_IN
TxGTM
DQ
CK Q
R
TMRx(2)
TMRxH
TMRxL
0
Single Pulse
1
Acq. Control
TxGGO/DONE
0
TxGVAL
DQ
1
Q1 EN
Interrupt
det
TMRxON
TMRxGE
Data Bus
RD
TXGCON
Set
TMRxGIF
EN
TxCLK
0
QD
Synchronized
clock input
TMRxCS<1:0>
1
TxSYNC
T1OSO/T1CKI
T1OSI
T1OSCEN
OUT
(6)
T1OSC
EN
Cap. Sense(5)
1 Oscillator A/B
11
10
0
FOSC
Internal
00
Clock
FOSC/4
Internal
00
Clock
Prescaler
1, 2, 4, 8
2
TxCKPS<1:0>
Synchronize(3)
det
FOSC/2
Internal
Clock
Sleep input
(1)
TxCKI
Note 1:
2:
3:
4:
5:
6:
ST Buffer is high speed type when using TxCKI.
Timer1/3 register increments on rising edge.
Synchronize does not operate while in Sleep.
Timer1 gate source is TimerA. Timer3 gate source is TimerB. Refer to Table 13-1.
Timer1 clock source is CPSAOSC. Timer3 clock source is CPSBOSC. Refer to Table 13-1.
Timer3 does not have a T3OSC circuit. There is no T3OSCEN bit. Timer3 can operate from T1OSC.
TABLE 13-1: CPSOSC/TIMER
ASSOCIATION
Period
Cap Sense
Measurement Oscillator
Divider Timer
(Gate Source)
Timer1
CPS A
TimerA
Timer3
CPS B
TimerB
DS41418A-page 100
Preliminary
ï£ 2010 Microchip Technology Inc.
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