PIC16F707 Datasheet, PDF (153/284 Pages) Microchip Technology – 40/44-Pin, Flash Microcontrollers with nanoWatt XLP and mTouch™ Technology

PIC16F707/PIC16LF707
FIGURE 18-8:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
RX/DT
pin
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
TX/CK pin
Write to
bit SREN
SREN bit
CREN bit ^{‘0’}
‘0’
RCIF bit
(Interrupt)
Read
RCREG
Note:
Timing diagram demonstrates Synchronous Master mode with bit SREN = 1 and bit BRGH = 0.
TABLE 18-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
ANSELC
INTCON
PIE1
PIR1
RCREG
RCSTA
TRISC
TXSTA
Legend:
ANSC7 ANSC6 ANSC5
—
—
ANSC2 ANSC1 ANSC0 111- -111 111- -111
GIE
PEIE TMR0IE INTE
RBIE TMR0IF INTF
RBIF 0000 000x 0000 000x
TMR1GIE ADIE
RCIE
TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
TMR1GIF ADIF
RCIF
TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
AUSART Receive Data Register
0000 0000 0000 0000
SPEN
RX9
SREN CREN ADDEN FERR OERR RX9D 0000 000X 0000 000X
TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111
CSRC
TX9
TXEN SYNC
—
BRGH TRMT TX9D 0000 -010 0000 -010
x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for synchronous master reception.
 2010 Microchip Technology Inc.
Preliminary
DS41418A-page 153