PIC16F707 Datasheet, PDF (183/284 Pages) Microchip Technology – 40/44-Pin, Flash Microcontrollers with nanoWatt XLP and mTouch™ Technology

PIC16F707/PIC16LF707
21.0 POWER-DOWN MODE (SLEEP)
The Power-down mode is entered by executing a
SLEEP instruction.
Upon entering Sleep mode, the following conditions
exist:
1. WDT will be cleared but keeps running, if
enabled.
2. PD bit of the STATUS register is cleared.
3. TO bit of the STATUS register is set.
4. CPU clock is disabled.
5. 31 kHz LFINTOSC is unaffected and peripherals
that operate from it may continue operation in
Sleep.
6. Timer1/3 oscillator is unaffected and peripherals
that operate from it may continue operation in
Sleep.
7. ADC is unaffected, if the dedicated FRC clock is
selected.
8. Capacitive Sensing oscillators are unaffected.
9. I/O ports maintain the status they had before
SLEEP was executed (driving high, low or high-
impedance).
10. Resets other than WDT are not affected by
Sleep mode.
Refer to individual chapters for more details on
peripheral operation during Sleep.
To minimize current consumption, the following
conditions should be considered:
• I/O pins should not be floating
• External circuitry sinking current from I/O pins
• Internal circuitry sourcing current from I/O pins
• Current draw from pins with internal weak pull-ups
• Modules using 31 kHz LFINTOSC
• Modules using Timer1/3 oscillator
I/O pins that are high-impedance inputs should be
pulled to VDD or VSS externally to avoid switching cur-
rents caused by floating inputs.
Examples of internal circuitry that might be sourcing
current include modules such as the DAC and FVR
modules. See Section 11.0 “Digital-to-Analog Con-
verter (DAC) Module” and Section 10.0 “Fixed Volt-
age Reference” for more information on these
modules.
21.1 Wake-up from Sleep
The device can wake-up from Sleep through one of the
following events:
1. External Reset input on MCLR pin, if enabled
2. BOR Reset, if enabled
3. POR Reset
4. Watchdog Timer, if enabled
5. Any external interrupt
6. Interrupts by peripherals capable of running
during Sleep (see individual peripheral for more
information)
The first three events will cause a device Reset. The
last three events are considered a continuation of
program execution.
When the SLEEP instruction is being executed, the next
instruction (PC + 1) is prefetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be enabled. Wake-up will
occur regardless of the state of the GIE bit. If the GIE
bit is disabled, the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
enabled, the device executes the instruction after the
SLEEP instruction, the device will call the Interrupt
Service Routine. In cases where the execution of the
instruction following SLEEP is not desirable, the user
should have a NOP after the SLEEP instruction.
The WDT is cleared when the device wakes up from
Sleep, regardless of the source of wake-up.
 2010 Microchip Technology Inc.
Preliminary
DS41418A-page 183