PIC16F707 Datasheet, PDF(61/284 Page) Microchip Technology – 40/44-Pin, Flash Microcontrollers with nanoWatt XLP and mTouch™ Technology

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

PIC16F707 Datasheet, PDF (61/284 Pages) Microchip Technology – 40/44-Pin, Flash Microcontrollers with nanoWatt XLP and mTouch™ Technology

◁

PIC16F707/PIC16LF707

6.4.2.3 RC2/CCP1/CPSB4/TBCKI

These pins are configurable to function as one of the

following:

â¢ General purpose I/O

â¢ Capture 1 input, Compare 1 output, and PWM1

output

â¢ Capacitive sensing input

â¢ TimerB Clock input

6.4.2.4 RC3/SCK/SCL

These pins are configurable to function as one of the

following:

â¢ General purpose I/O

â¢ SPI clock

â¢ I2Câ¢ clock

6.4.2.5 RC4/SDI/SDA

These pins are configurable to function as one of the

following:

â¢ General purpose I/O

â¢ SPI data input

â¢ I2C data I/O

6.4.2.6 RC5/SDO/CPSA9

These pins are configurable to function as one of the

following:

â¢ General purpose I/O

â¢ SPI data output

â¢ Capacitive sensing input

6.4.2.7 RC6/TX/CK/CPSA10

These pins are configurable to function as one of the

following:

â¢ General purpose I/O

â¢ Asynchronous serial output

â¢ Synchronous clock I/O

â¢ Capacitive sensing input

6.4.2.8 RC7/RX/DT/CPSA11

These pins are configurable to function as one of the

following:

â¢ General purpose I/O

â¢ Asynchronous serial input

â¢ Synchronous serial data I/O

â¢ Capacitive sensing input

TABLE 6-3: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Value on all

other

Resets

ANSELC

APFCON

CCP1CON

CCP2CON

CPSACON0

CPSACON1

CPSBCON0

CPSBCON1

PORTC

RCSTA

SSPCON

SSPSTAT

T1CON

TBCON

TXSTA

TRISC

Legend:

ANSC7 ANSC6 ANSC5

â

â

ANSC2

ANSC1 ANSC0 111- -111 111- -111

â

â

â

â

â

â

SSSEL CCP2SEL ---- --00 ---- --00

â

â

DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000

â

â

DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000

CPSAON CPSARM

â

â

CPSARNG1 CPSARNG0 CPSAOUT TAXCS 00-- 0000 00-- 0000

â

â

â

â

CPSACH3 CPSACH2 CPSACH1 CPSACH0 ---- 0000 ---- 0000

CPSBON CPSBRM

â

â

CPSBRNG1 CPSBRNG0 CPSBOUT TBXCS 00-- 0000 00-- 0000

â

â

â

â

CPSBCH3 CPSBCH2 CPSBCH1 CPSBCH0 ---- 0000 ---- 0000

RC7

RC6

RC5

RC4

RC3

RC2

RC1

RC0 xxxx xxxx xxxx xxxx

SPEN

RX9

SREN

CREN

ADDEN

FERR

OERR

RX9D 0000 000x 0000 000x

WCOL

SSPOV SSPEN

CKP

SSPM3

SSPM2

SSPM1 SSPM0 0000 0000 0000 0000

SMP

CKE

D/A

P

S

R/W

UA

BF

0000 0000 0000 0000

TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC

â

TMR1ON 0000 00-0 uuuu uu-u

TMRBON

â

TBCS

TBSE

TBPSA

TBPS2

TBPS1

TBPS0 0-00 0000 0-00 0000

CSRC

TX9

TXEN

SYNC

â

BRGH

TRMT

TX9D 0000 -010 0000 -010

TRISC7 TRISC6 TRISC5 TRISC4 TRISC3

TRISC2

TRISC1 TRISC0 1111 1111 1111 1111

x = unknown, u = unchanged, - = unimplemented locations read as â0â. Shaded cells are not used by PORTC.

ï£ 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 61

▷