PIC16F707 Datasheet, PDF (54/284 Pages) Microchip Technology – 40/44-Pin, Flash Microcontrollers with nanoWatt XLP and mTouch™ Technology

PIC16F707/PIC16LF707
6.2.2.4 RA3/AN3/VREF+/CPSA2
The RA3 pin is configurable to function as one of the
following:
• General purpose I/O
• Analog input for the A/D
• Voltage Reference input for the A/D
• Capacitive sensing input
6.2.2.5 RA4/CPSA3/T0CKI/TACKI
The RA4 pin is configurable to function as one of the
following:
• General purpose I/O
• Capacitive sensing input
• Clock input for Timer0
• Clock input for TimerA
The Timer0 clock input function works independently
of any TRIS register setting. Effectively, if TRISA4 = 0,
the PORTA4 register bit will output to the pad and
clock Timer0 at the same time.
6.2.2.7 RA6/CPSB1/OSC2/CLKOUT/VCAP
The RA6 pin is configurable to function as one of the
following:
• General purpose I/O
• Crystal/resonator connection
• Clock Output
• Voltage Regulator Capacitor pin (PIC16F707
only)
• Capacitive sensing input
6.2.2.8 RA7/CPSB0/OSC1/CLKIN
The RA7 pin is configurable to function as one of the
following:
• General purpose I/O
• Crystal/resonator connection
• Clock Input
• Capacitive sensing input.
6.2.2.6 RA5/AN4/CPSA4/SS/VCAP
The RA5 pin is configurable to function as one of the
following:
• General purpose I/O
• Capacitive sensing input
• Analog input for the A/D
• Slave Select input for the SSP⁽¹⁾
• Voltage Regulator Capacitor pin (PIC16F707
only)
Note 1: SS pin location may be selected as RA5
or RA0.
TABLE 6-1: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
ADCON0
—
—
CHS3 CHS2
CHS1
CHS0
GO/DONE ADON --00 0000
ADCON1
—
ADCS2 ADCS1 ADCS0
—
—
ADREF1 ADREF0 -000 --00
ANSELA
ANSA7
ANSA6 ANSA5 ANSA4
ANSA3
ANSA2
ANSA1 ANSA0 1111 1111
APFCON
—
—
—
—
—
—
SSSEL CCP2SEL ---- --00
CPSACON0
CPSAON CPSARM
—
—
CPSARNG1 CPSARNG0 CPSAOUT TAXCS 00-- 0000
CPSACON1
—
—
—
—
CPSACH3 CPSACH2 CPSACH1 CPSACH0 ---- 0000
CPSBCON0
CPSBON CPSBRM
—
—
CPSBRNG1 CPSBRNG0 CPSBOUT TBXCS 00-- 0000
CPSBCON1
—
CONFIG2⁽¹⁾
—
—
—
—
CPSBCH3 CPSBCH2 CPSBCH1 CPSBCH0 ---- 0000
—
VCAPEN1 VCAPEN0
—
—
—
—
—
OPTION_REG RBPU
INTEDG TMR0CS TMR0SE
PSA
PS2
PS1
PS0
1111 1111
PORTA
RA7
RA6
RA5
RA4
RA3
RA2
RA1
RA0
xxxx xxxx
SSPCON
WCOL
SSPOV SSPEN CKP
SSPM3
SSPM2
SSPM1 SSPM0 0000 0000
TRISA
TRISA7 TRISA6 TRISA5 TRISA4 TRISA3
TRISA2
TRISA1 TRISA0 1111 1111
TACON
TMRAON
—
TACS TASE
TAPSA
TAPS2
TAPS1
TAPS0 0-00 0000
DACCON0
DACEN DACLPS DACOE
—
DACPSS1 DACPSS0
—
—
000- 00--
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.
Note 1: PIC16F707 only.
Value on
all other
Resets
--00 0000
-000 --00
1111 1111
---- --00
00-- 0000
---- 0000
00-- 0000
---- 0000
—
1111 1111
xxxx xxxx
0000 0000
1111 1111
0-00 0000
000- 00--
DS41418A-page 54
Preliminary
 2010 Microchip Technology Inc.