PIC16F707 Datasheet, PDF (103/284 Pages) Microchip Technology – 40/44-Pin, Flash Microcontrollers with nanoWatt XLP and mTouch™ Technology

PIC16F707/PIC16LF707
TABLE 13-5: TIMER1/3 GATE SOURCES
TxGSS
Timer1 Gate Source
00 Timer1 Gate Pin
01 Overflow of TimerA
(TMRA increments from FFh to 00h)
10 Timer2 match PR2
(TMR2 increments to match PR2)
11 Count Enabled by WDT Overflow
(Watchdog Time-out interval expired)
13.6.3 TxG PIN GATE OPERATION
The TxG pin is one source for Timer1/3 gate control.
It can be used to supply an external source to the
Timer1/3 gate circuitry. Timer1 gate can be configured
for the T1G pin and Timer3 gate can be configured for
the T3G pin.
13.6.4 TIMERA/B OVERFLOW GATE
OPERATION
When TimerA/B increments from FFh to 00h a low-to-
high pulse will automatically be generated and
internally supplied to the Timer1/3 gate circuitry. Timer1
gate can be configured for TimerA overflow and Timer3
gate can be configured for TimerB overflow.
13.6.5 TIMER2 MATCH GATE OPERATION
The TMR2 register will increment until it matches the
value in the PR2 register. On the very next increment
cycle, TMR2 will be reset to 00h. When this Reset
occurs, a low-to-high pulse will automatically be gener-
ated and internally supplied to the Timer1/3 gate cir-
cuitry. Both Timer1 gate and Timer3 gate can be
configured for the Timer2 match.
Timer3 Gate Source
Timer3 Gate Pin
Overflow of TimerB
(TMRB increments from FFh to 00h)
Timer2 match PR2
(TMR2 increments to match PR2)
Count Enabled by WDT Overflow
(Watchdog Time-out interval expired)
13.6.6 WATCHDOG OVERFLOW GATE
OPERATION
The Watchdog Timer oscillator, prescaler and counter
will be automatically turned on when TMRxGE = 1 and
TxGSS selects the WDT as a gate source for Timer1/3
(TxGSS = 11). TMRxON does not factor into the oscil-
lator, prescaler and counter enable. See Table 13-6.
Both Timer1 gate and Timer3 gate can be configured
for Watchdog overflow.
The PSA and PS bits of the OPTION register still
control what time-out interval is selected. Changing the
prescaler during operation may result in a spurious
capture.
Enabling the Watchdog Timer oscillator does not
automatically enable a Watchdog Reset or wake-up
from Sleep upon counter overflow.
Note:
When using the WDT as a gate source for
Timer1/3, operations that clear the
Watchdog Timer (CLRWDT, SLEEP
instructions) will affect the time interval
being measured for capacitive sensing.
This includes waking from Sleep. All other
interrupts that might wake the device from
Sleep should be disabled to prevent them
from disturbing the measurement period.
As the gate signal coming from the WDT counter will
generate different pulse widths, depending on if the
WDT is enabled, when the CLRWDT instruction is exe-
cuted, and so on, Toggle mode must be used. A spe-
cific sequence is required to put the device into the
correct state to capture the next WDT counter interval.
TABLE 13-6: WDT/TIMER1/3 GATE INTERRACTION
WDTE
TMRxGE = 1 and WDT Oscillator
TxGSS = 11
Enable
WDT Reset
1
N
Y
Y
1
Y
Y
Y
0
Y
Y
N
0
N
N
N
Wake-up
Y
Y
N
N
WDT Available for
TxG Source
N
Y
Y
N
 2010 Microchip Technology Inc.
Preliminary
DS41418A-page 103