PIC16F707 Datasheet, PDF (129/284 Pages) Microchip Technology – 40/44-Pin, Flash Microcontrollers with nanoWatt XLP and mTouch™ Technology

PIC16F707/PIC16LF707
17.1 Capture Mode
In Capture mode, CCPRxH:CCPRxL captures the
16-bit value of the TMR1 register when an event occurs
on pin CCPx. An event is defined as one of the
following and is configured by the CCPxM<3:0> bits of
the CCPxCON register:
• Every falling edge
• Every rising edge
• Every 4th rising edge
• Every 16th rising edge
When a capture is made, the interrupt request flag bit
CCPxIF of the PIRx register is set. The interrupt flag
must be cleared in software. If another capture occurs
before the value in the CCPRxH, CCPRxL register pair
is read, the old captured value is overwritten by the new
captured value (refer to Figure 17-1).
17.1.1 CCPx PIN CONFIGURATION
In Capture mode, the CCPx pin should be configured
as an input by setting the associated TRIS control bit.
Either RC1 or RB3 can be selected as the CCP2 pin.
Refer to Section 6.1 “Alternate Pin Function” for
more information.
Note:
If the CCPx pin is configured as an output,
a write to the port can cause a capture
condition.
FIGURE 17-1:
CAPTURE MODE
OPERATION BLOCK
DIAGRAM
CCPx
Set Flag bit CCPxIF
Prescaler ^{(PIRx register)}
 1, 4, 16
CCPRxH
CCPRxL
and
Edge Detect
Capture
Enable
TMR1H
CCPxCON<3:0>
System Clock (FOSC)
TMR1L
17.1.2 TIMER1 MODE SELECTION
Timer1 must be running in Timer mode or Synchronized
Counter mode for the CCP module to use the capture
feature. In Asynchronous Counter mode or when
Timer1 is clocked at FOSC, the capture operation may
not work.
17.1.3 SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep the
CCPxIE interrupt enable bit of the PIEx register clear to
avoid false interrupts. Additionally, the user should
clear the CCPxIF interrupt flag bit of the PIRx register
following any change in operating mode.
Note:
Clocking Timer1 from the system clock
(FOSC) should not be used in Capture
mode. In order for Capture mode to
recognize the trigger event on the CCPx
pin, Timer1 must be clocked from the
instruction clock (FOSC/4) or from an
external clock source.
17.1.4 CCP PRESCALER
There are four prescaler settings specified by the
CCPxM<3:0> bits of the CCPxCON register. Whenever
the CCP module is turned off, or the CCP module is not
in Capture mode, the prescaler counter is cleared. Any
Reset will clear the prescaler counter.
Switching from one capture prescaler to another does not
clear the prescaler and may generate a false interrupt. To
avoid this unexpected operation, turn the module off by
clearing the CCPxCON register before changing the
prescaler (refer to Example 17-1).
EXAMPLE 17-1: CHANGING BETWEEN
CAPTURE PRESCALERS
BANKSEL CCP1CON ;Set Bank bits to point
;to CCP1CON
CLRF CCP1CON ;Turn CCP module off
MOVLW NEW_CAPT_PS ;Load the W reg with
; the new prescaler
; move value and CCP ON
MOVWF CCP1CON ;Load CCP1CON with this
; value
17.1.5 CAPTURE DURING SLEEP
Capture mode depends upon the Timer1 module for
proper operation. There are two options for driving the
Timer1 module in Capture mode. It can be driven by
the instruction clock (FOSC/4), or by an external clock
source.
If Timer1 is clocked by FOSC/4, then Timer1 will not
increment during Sleep. When the device wakes from
Sleep, Timer1 will continue from its previous state.
If Timer1 is clocked by an external clock source, then
Capture mode will operate as defined in Section 17.1
“Capture Mode”.
 2010 Microchip Technology Inc.
Preliminary
DS41418A-page 129