PIC16F707 Datasheet, PDF (44/284 Pages) Microchip Technology – 40/44-Pin, Flash Microcontrollers with nanoWatt XLP and mTouch™ Technology

PIC16F707/PIC16LF707
4.5.3 PIE2 REGISTER
The PIE2 register contains the interrupt enable bits, as
shown in Register 4-3.
Note: Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
REGISTER 4-3: PIE2 – PERIPHERAL INTERRUPT ENABLE REGISTER 2
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
TMR3GIE
TMR3IE
TMRBIE
TMRAIE
—
—
—
bit 7
R/W-0
CCP2IE
bit 0
Legend:
R = Readable bit
u = bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other
Resets
bit 7
bit 6
bit 5
bit 4
bit 3-1
bit 0
TMR3GIE: Timer3 Gate Interrupt Flag bit
1 = Enable the Timer3 gate acquisition complete interrupt
0 = Disable the Timer3 gate acquisition complete interrupt
TMR3IE: Timer3 Overflow Interrupt Enable bit
1 = Enables the Timer3 overflow interrupt
0 = Disables the Timer3 overflow interrupt
TMRBIE: TimerB Overflow Interrupt Enable bit
1 = Enables the TimerB interrupt
0 = Disables the TimerB interrupt
TMRAIE: TimerA Overflow Interrupt Enable bit
1 = Enables the TimerA interrupt
0 = Disables the TimerA interrupt
Unimplemented: Read as '0'
CCP2IE: CCP2 Interrupt Enable bit
1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt
DS41418A-page 44
Preliminary
 2010 Microchip Technology Inc.