PIC16F707 Datasheet, PDF (21/284 Pages) Microchip Technology – 40/44-Pin, Flash Microcontrollers with nanoWatt XLP and mTouch™ Technology

PIC16F707/PIC16LF707
TABLE 2-2: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on all
other
resets
Bank 2
100h^{( 2)} INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
xxxx xxxx xxxx xxxx
101h
102h^{( 2)}
103h^{( 2)}
104h^{( 2)}
TMR0
PCL
STATUS
FSR
Timer0 Module Register
Program Counter’s (PC) Least Significant Byte
IRP
RP1
RP0
TO
PD
Z
DC
Indirect Data Memory Address Pointer
0000 0000 0000 0000
0000 0000 0000 0000
C
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
105h
TACON
TMRAON
—
TACS
TASE
TAPSA
TAPS2
TAPS1
TAPS0 0-00 0000 0-00 0000
106h
CPSBCON0 CPSBON CPSBRM
—
—
CPSBRNG1 CPSBRNG0 CPSBOUT TBXCS 00-- 0000 00-- 0000
107h
CPSBCON1
—
—
—
—
CPSBCH3 CPSBCH2 CPSBCH1 CPSBCH0 ---- 0000 ---- 0000
108h
CPSACON0 CPSAON CPSARM
—
—
CPSARNG1 CPSARNG0 CPSAOUT TAXCS 0--- 0000 0--- 0000
109h
CPSACON1
—
—
—
—
CPSACH3 CPSACH2 CPSACH1 CPSACH0 ---- 0000 ---- 0000
10Ah^{( 1),(2)} PCLATH
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
---0 0000 ---0 0000
10Bh^{( 2)} INTCON
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF 0000 000x 0000 000u
10Ch
PMDATL
Program Memory Read Data Register Low Byte
xxxx xxxx uuuu uuuu
10Dh
PMADRL
Program Memory Read Address Register Low Byte
xxxx xxxx uuuu uuuu
10Eh
PMDATH
—
—
Program Memory Read Data Register High Byte
--xx xxxx --uu uuuu
10Fh
PMADRH
—
—
—
Program Memory Read Address Register High Byte
---x xxxx ---u uuuu
110h
TMRA
TimerA Module Register
0000 0000 0000 0000
111h
TBCON
TMRBON
—
TBCS
TBSE
TBPSA
TBPS2
TBPS1
TBPS0 0-00 0000 0-00 0000
112h
TMRB
TimerB Module Register
0000 0000 0000 0000
113h
DACCON0
DACEN DACLPS DACOE
—
DACPSS1 DACPSS0
—
—
000- 00-- 000- 00--
114h
DACCON1
—
—
—
DACR4
DACR3
DACR2
DACR1 DACR0 ---0 0000 ---0 0000
Legend:
Note 1:
2:
3:
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the
upper byte of the program counter.
These registers can be addressed from any bank.
Accessible only when SSPM<3:0> = 1001.
 2010 Microchip Technology Inc.
Preliminary
DS41418A-page 21