PIC16F707 Datasheet, PDF (158/284 Pages) Microchip Technology – 40/44-Pin, Flash Microcontrollers with nanoWatt XLP and mTouch™ Technology

PIC16F707/PIC16LF707
FIGURE 19-2:
SPI MODE BLOCK
DIAGRAM
Read
Internal
Data Bus
Write
SSPBUF Reg
SDI
SDO
RA5/SS
RA0/SS
SSPSR Reg
bit 0
Shift ^{bit 7}
Clock
SS
Control
Enable
SSSEL
Edge
Select
SCK
TRISx
2
Clock Select
Edge
Select
4
2
TMR2
Output
Prescaler FOSC
4, 16, 64
SSPM<3:0>
19.1.1 MASTER MODE
In Master mode, data transfer can be initiated at any
time because the master controls the SCK line. Master
mode determines when the slave (Figure 19-1,
Processor 2) transmits data via control of the SCK line.
19.1.1.1 Master Mode Operation
The SSP consists of a transmit/receive shift register
(SSPSR) and a buffer register (SSPBUF). The SSPSR
register shifts the data in and out of the device, MSb
first. The SSPBUF register holds the data that is written
out of the master until the received data is ready. Once
the eight bits of data have been received, the byte is
moved to the SSPBUF register. The Buffer Full Status
bit, BF of the SSPSTAT register, and the SSP Interrupt
Flag bit, SSPIF of the PIR1 register, are then set.
Any write to the SSPBUF register during transmission/
reception of data will be ignored and the Write Collision
Detect bit, WCOL of the SSPCON register, will be set.
User software must clear the WCOL bit so that it can be
determined if the following write(s) to the SSPBUF
register completed successfully.
When the application software is expecting to receive
valid data, the SSPBUF should be read before the next
byte of data is written to the SSPBUF. The BF bit of the
SSPSTAT register is set when SSPBUF has been
loaded with the received data (transmission is
complete). When the SSPBUF is read, the BF bit is
cleared. This data may be irrelevant if the SPI is only a
transmitter. The SSP interrupt may be used to
determine when the transmission/reception is
complete and the SSPBUF must be read and/or
written. If interrupts are not used, then software polling
can be done to ensure that a write collision does not
occur. Example 19-1 shows the loading of the SSPBUF
(SSPSR) for data transmission.
Note:
The SSPSR is not directly readable or
writable and can only be accessed by
addressing the SSPBUF register.
19.1.1.2 Enabling Master I/O
To enable the serial port, the SSPEN bit of the
SSPCON register, must be set. To reset or reconfigure
SPI mode, clear the SSPEN bit, re-initialize the
SSPCON register and then set the SSPEN bit. If a
Master mode of operation is selected in the SSPM bits
of the SSPCON register, the SDI, SDO and SCK pins
will be assigned as serial port pins.
For these pins to function as serial port pins, they must
have their corresponding data direction bits set or
cleared in the associated TRIS register as follows:
• SDI configured as input
• SDO configured as output
• SCK configured as output
DS41418A-page 158
Preliminary
 2010 Microchip Technology Inc.